A low noise and low power CMOS image sensor with pixel-level correlated double sampling

Dongsoo Kim; Gunhee Han

doi:10.1109/DDECS.2007.4295263

A low noise and low power CMOS image sensor with pixel-level correlated double sampling

Dongsoo Kim, Gunhee Han

School of Integrated Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

A Low noise and low power CMOS Image Sensor (CIS) with pixel-level Correlated Double Sampling (CDS) is proposed. As the pixel readout circuit using source follower is major readout noise and power consumption source in the conventional CIS structure, the proposed new structure removes the source follower and performs pixel-level CDS and comparing. The proposed CIS is integrated with 240×180 pixel array. A pixel fill factor is 32% and its pitch is 8.4μm. The test chip was fabricated with CMOS 0.35-μm process and its power consumption is 18 mW with 3.3 V occupying 8.1 mm²

Original language	English
Title of host publication	Proceedings of the 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS
Pages	113-115
Number of pages	3
DOIs	https://doi.org/10.1109/DDECS.2007.4295263
Publication status	Published - 2007
Event	2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS - Krakow, Poland Duration: 2007 Apr 11 → 2007 Apr 13

Publication series

Name	Proceedings of the 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS

Other

Other	2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS
Country/Territory	Poland
City	Krakow
Period	07/4/11 → 07/4/13

All Science Journal Classification (ASJC) codes

Control and Systems Engineering
Electrical and Electronic Engineering

Access to Document

10.1109/DDECS.2007.4295263

Cite this

Kim, D., & Han, G. (2007). A low noise and low power CMOS image sensor with pixel-level correlated double sampling. In Proceedings of the 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS (pp. 113-115). Article 4295263 (Proceedings of the 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS). https://doi.org/10.1109/DDECS.2007.4295263

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title = "A low noise and low power CMOS image sensor with pixel-level correlated double sampling",

abstract = "A Low noise and low power CMOS Image Sensor (CIS) with pixel-level Correlated Double Sampling (CDS) is proposed. As the pixel readout circuit using source follower is major readout noise and power consumption source in the conventional CIS structure, the proposed new structure removes the source follower and performs pixel-level CDS and comparing. The proposed CIS is integrated with 240×180 pixel array. A pixel fill factor is 32% and its pitch is 8.4μm. The test chip was fabricated with CMOS 0.35-μm process and its power consumption is 18 mW with 3.3 V occupying 8.1 mm2",

author = "Dongsoo Kim and Gunhee Han",

year = "2007",

doi = "10.1109/DDECS.2007.4295263",

language = "English",

isbn = "1424411610",

series = "Proceedings of the 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS",

pages = "113--115",

booktitle = "Proceedings of the 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS",

note = "2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS ; Conference date: 11-04-2007 Through 13-04-2007",

}

Kim, D & Han, G 2007, A low noise and low power CMOS image sensor with pixel-level correlated double sampling. in Proceedings of the 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS., 4295263, Proceedings of the 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS, pp. 113-115, 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS, Krakow, Poland, 07/4/11. https://doi.org/10.1109/DDECS.2007.4295263

A low noise and low power CMOS image sensor with pixel-level correlated double sampling. / Kim, Dongsoo; Han, Gunhee.
Proceedings of the 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS. 2007. p. 113-115 4295263 (Proceedings of the 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - A Low noise and low power CMOS Image Sensor (CIS) with pixel-level Correlated Double Sampling (CDS) is proposed. As the pixel readout circuit using source follower is major readout noise and power consumption source in the conventional CIS structure, the proposed new structure removes the source follower and performs pixel-level CDS and comparing. The proposed CIS is integrated with 240×180 pixel array. A pixel fill factor is 32% and its pitch is 8.4μm. The test chip was fabricated with CMOS 0.35-μm process and its power consumption is 18 mW with 3.3 V occupying 8.1 mm2

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Kim D, Han G. A low noise and low power CMOS image sensor with pixel-level correlated double sampling. In Proceedings of the 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS. 2007. p. 113-115. 4295263. (Proceedings of the 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS). doi: 10.1109/DDECS.2007.4295263

A low noise and low power CMOS image sensor with pixel-level correlated double sampling

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