TY - GEN
T1 - A low-cost DDEM ADC structure for the testing of high-performance DACs
AU - Jang, Jaewon
AU - Kim, Incheol
AU - Son, Hyeonuk
AU - Kang, Sungho
PY - 2011
Y1 - 2011
N2 - The testing of high resolution and high speed DACs (Digital-to-Analog Converters) is extremely challenging because of the requirements on the accuracy, speed and cost. This paper presents a new hardware overhead reduction method using DDEM (Deterministic Dynamic Element Matching) techniques for the testing of DACs. In this work, the proposed method make that resistors in a resistor string have different lengths by a merging operation. Accuracy of the proposed method is proven by theoretical analysis. The experimental results show that the proposed method reduces the usage of resources over 17%.
AB - The testing of high resolution and high speed DACs (Digital-to-Analog Converters) is extremely challenging because of the requirements on the accuracy, speed and cost. This paper presents a new hardware overhead reduction method using DDEM (Deterministic Dynamic Element Matching) techniques for the testing of DACs. In this work, the proposed method make that resistors in a resistor string have different lengths by a merging operation. Accuracy of the proposed method is proven by theoretical analysis. The experimental results show that the proposed method reduces the usage of resources over 17%.
UR - http://www.scopus.com/inward/record.url?scp=80053631986&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=80053631986&partnerID=8YFLogxK
U2 - 10.1109/MWSCAS.2011.6026360
DO - 10.1109/MWSCAS.2011.6026360
M3 - Conference contribution
AN - SCOPUS:80053631986
SN - 9781612848570
T3 - Midwest Symposium on Circuits and Systems
BT - 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
T2 - 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
Y2 - 7 August 2011 through 10 August 2011
ER -