This paper proposes a column-parallel two-step single-slope (SS) ADC for high-speed CMOS image sensors. Error correction scheme to improve the linearity is proposed as well. A prototype sensor of 320 × 240 pixels has been fabricated with a 0.35-μm CMOS process. Measurement results demonstrate that the proposed ADC can achieve the conversion time of 4 μs, which is ten times faster than the conventional SS ADC. The proposed error correction effectively removes the dead band problem and yields DNL of +0.53/ -0.78 LSB and INL of +1.42/ -1.61 LSB. The power consumption is 36 mW from a supply voltage of 2.8 V.
Bibliographical noteFunding Information:
Manuscript received September 5, 2008; revised November 25, 2008. Current version published February 25, 2009. This work was supported in part by the MKE (Ministry of Knowledge Economy), Korea, under the ITRC (Information Technology Research Center) support program supervised by the IITA (Institute of Information Technology Advancement) (IITA-2008-(C1090-0801-0012)) and in part by Samsung Electronics Co., Ltd. The review of this paper was arranged by Editor J. Tower.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering