A high-level signal integrity fault model and test methodology for long on-chip interconnections

Sunghoon Chun; Yongjoon Kim; Taejin Kim; Sungho Kang

doi:10.1109/VTS.2009.38

A high-level signal integrity fault model and test methodology for long on-chip interconnections

Sunghoon Chun, Yongjoon Kim, Taejin Kim, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper, considering the interconnection topology information, an abstract model and a new test pattern generation method of signal integrity problems on interconnects are proposed. In addition, previous SPICE-based pattern generation methods are too complex and time consuming to generate test patterns for signal integrity faults. To more accurately detect signal integrity defects on practical on-chip interconnection lines and avoid time consuming for interconnection analysis, in this paper, we propose a new high-level signal integrity fault model to estimate noise effects based on process variation and interconnect signal transition. Experimental results show that the proposed signal integrity fault model is more exact for long interconnects than previous approaches. In addition, the proposed method is much faster than the SPICE-based pattern generation method.

Original language	English
Title of host publication	Proceedings - 2009 27th IEEE VLSI Test Symposium, VTS 2009
Pages	152-157
Number of pages	6
DOIs	https://doi.org/10.1109/VTS.2009.38
Publication status	Published - 2009
Event	2009 27th IEEE VLSI Test Symposium, VTS 2009 - Santa Cruz, CA, United States Duration: 2009 May 3 → 2009 May 7

Publication series

Name	Proceedings of the IEEE VLSI Test Symposium

Other

Other	2009 27th IEEE VLSI Test Symposium, VTS 2009
Country/Territory	United States
City	Santa Cruz, CA
Period	09/5/3 → 09/5/7

All Science Journal Classification (ASJC) codes

Computer Science Applications
Electrical and Electronic Engineering

Access to Document

10.1109/VTS.2009.38

Cite this

@inproceedings{e71c14b27c5a4133a806298bffd77731,

title = "A high-level signal integrity fault model and test methodology for long on-chip interconnections",

abstract = "In this paper, considering the interconnection topology information, an abstract model and a new test pattern generation method of signal integrity problems on interconnects are proposed. In addition, previous SPICE-based pattern generation methods are too complex and time consuming to generate test patterns for signal integrity faults. To more accurately detect signal integrity defects on practical on-chip interconnection lines and avoid time consuming for interconnection analysis, in this paper, we propose a new high-level signal integrity fault model to estimate noise effects based on process variation and interconnect signal transition. Experimental results show that the proposed signal integrity fault model is more exact for long interconnects than previous approaches. In addition, the proposed method is much faster than the SPICE-based pattern generation method.",

author = "Sunghoon Chun and Yongjoon Kim and Taejin Kim and Sungho Kang",

year = "2009",

doi = "10.1109/VTS.2009.38",

language = "English",

isbn = "9780769535982",

series = "Proceedings of the IEEE VLSI Test Symposium",

pages = "152--157",

booktitle = "Proceedings - 2009 27th IEEE VLSI Test Symposium, VTS 2009",

note = "2009 27th IEEE VLSI Test Symposium, VTS 2009 ; Conference date: 03-05-2009 Through 07-05-2009",

}

Chun, S, Kim, Y, Kim, T & Kang, S 2009, A high-level signal integrity fault model and test methodology for long on-chip interconnections. in Proceedings - 2009 27th IEEE VLSI Test Symposium, VTS 2009., 5116626, Proceedings of the IEEE VLSI Test Symposium, pp. 152-157, 2009 27th IEEE VLSI Test Symposium, VTS 2009, Santa Cruz, CA, United States, 09/5/3. https://doi.org/10.1109/VTS.2009.38

A high-level signal integrity fault model and test methodology for long on-chip interconnections. / Chun, Sunghoon; Kim, Yongjoon; Kim, Taejin et al.
Proceedings - 2009 27th IEEE VLSI Test Symposium, VTS 2009. 2009. p. 152-157 5116626 (Proceedings of the IEEE VLSI Test Symposium).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A high-level signal integrity fault model and test methodology for long on-chip interconnections

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N2 - In this paper, considering the interconnection topology information, an abstract model and a new test pattern generation method of signal integrity problems on interconnects are proposed. In addition, previous SPICE-based pattern generation methods are too complex and time consuming to generate test patterns for signal integrity faults. To more accurately detect signal integrity defects on practical on-chip interconnection lines and avoid time consuming for interconnection analysis, in this paper, we propose a new high-level signal integrity fault model to estimate noise effects based on process variation and interconnect signal transition. Experimental results show that the proposed signal integrity fault model is more exact for long interconnects than previous approaches. In addition, the proposed method is much faster than the SPICE-based pattern generation method.

AB - In this paper, considering the interconnection topology information, an abstract model and a new test pattern generation method of signal integrity problems on interconnects are proposed. In addition, previous SPICE-based pattern generation methods are too complex and time consuming to generate test patterns for signal integrity faults. To more accurately detect signal integrity defects on practical on-chip interconnection lines and avoid time consuming for interconnection analysis, in this paper, we propose a new high-level signal integrity fault model to estimate noise effects based on process variation and interconnect signal transition. Experimental results show that the proposed signal integrity fault model is more exact for long interconnects than previous approaches. In addition, the proposed method is much faster than the SPICE-based pattern generation method.

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BT - Proceedings - 2009 27th IEEE VLSI Test Symposium, VTS 2009

T2 - 2009 27th IEEE VLSI Test Symposium, VTS 2009

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ER -

A high-level signal integrity fault model and test methodology for long on-chip interconnections

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