Abstract
The number of weighted random patterns depends on the number of deterministic test patterns with a low sampling probability. The weight set that is extracted from the deterministic pattern set with high sampling probability reduces the number of test patterns. In the basis, in this paper we present a new deterministic pattern selection algorithm which generates high performance weight sets by removing deterministic patterns with low sampling frequencies. Simulation results using ISCAS 85 benchmark circuits prove the effectiveness of the new weight set generation algorithm.
| Original language | English |
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| Pages | 513-514 |
| Number of pages | 2 |
| Publication status | Published - 2001 |
| Event | IEEE International Conference on: Computer Design: VLSI in Computers and Processors (ICCD 2001) - Austin, TX, United States Duration: 2001 Sept 23 → 2001 Sept 26 |
Other
| Other | IEEE International Conference on: Computer Design: VLSI in Computers and Processors (ICCD 2001) |
|---|---|
| Country/Territory | United States |
| City | Austin, TX |
| Period | 01/9/23 → 01/9/26 |
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering