A Hardware Architecture for the Affine-Invariant Extension of SIFT

Joohyuk Yum; Chul Hee Lee; Jinwoo Park; Jin Sung Kim; Hyuk Jae Lee

doi:10.1109/TCSVT.2017.2740175

A Hardware Architecture for the Affine-Invariant Extension of SIFT

Joohyuk Yum, Chul Hee Lee, Jinwoo Park, Jin Sung Kim, Hyuk Jae Lee

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

5 Citations (Scopus)

Abstract

Affine-invariant extension of scale-invariant feature transform (ASIFT) algorithm requires a large amount of computation and memory access, and consequently, is hard to process in real time. In order to increase the operation speed of ASIFT algorithm, this paper proposes a new hardware architecture for the ASIFT algorithm. In order to reduce the memory access time, the affine transform is modified to allow external memory access in the raster-scan order with a little accuracy drop. In addition, image filtering with skewed kernel is proposed in order to reduce the memory space for image storage. Additional complexity reduction is attempted to reduce the number of simulated viewpoints. As a result, throughput of the affine transform module is increased to 325% and the proposed hardware processes a video graphics array-sized (640×480) video at 20 fps.

Original language	English
Article number	8010882
Pages (from-to)	3251-3261
Number of pages	11
Journal	IEEE Transactions on Circuits and Systems for Video Technology
Volume	28
Issue number	11
DOIs	https://doi.org/10.1109/TCSVT.2017.2740175
Publication status	Published - 2018 Nov

Bibliographical note

Funding Information:
Manuscript received November 14, 2016; revised July 11, 2017; accepted July 29, 2017. Date of publication August 15, 2017; date of current version November 5, 2018. This work was supported in part by Samsung electronics and in part by the Korea Institute for Advancement of Technology grant funded by the Korean government (Ministry of Trade, Industry and Energy, HRD Program for Software-SoC convergence) under Grant N0001883. This paper was recommended by Associate Editor P. K. Meher. (Corresponding author: Jin-Sung Kim.) J. Yum is with the System LSI Division, Samsung Electronics Corporation, Hwaseong 18448, South Korea.

Publisher Copyright:
© 1991-2012 IEEE.

All Science Journal Classification (ASJC) codes

Media Technology
Electrical and Electronic Engineering

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10.1109/TCSVT.2017.2740175

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@article{8cb599e4e1834c768e79eae5121b24ee,

title = "A Hardware Architecture for the Affine-Invariant Extension of SIFT",

abstract = "Affine-invariant extension of scale-invariant feature transform (ASIFT) algorithm requires a large amount of computation and memory access, and consequently, is hard to process in real time. In order to increase the operation speed of ASIFT algorithm, this paper proposes a new hardware architecture for the ASIFT algorithm. In order to reduce the memory access time, the affine transform is modified to allow external memory access in the raster-scan order with a little accuracy drop. In addition, image filtering with skewed kernel is proposed in order to reduce the memory space for image storage. Additional complexity reduction is attempted to reduce the number of simulated viewpoints. As a result, throughput of the affine transform module is increased to 325% and the proposed hardware processes a video graphics array-sized (640×480) video at 20 fps.",

author = "Joohyuk Yum and Lee, {Chul Hee} and Jinwoo Park and Kim, {Jin Sung} and Lee, {Hyuk Jae}",

note = "Funding Information: Manuscript received November 14, 2016; revised July 11, 2017; accepted July 29, 2017. Date of publication August 15, 2017; date of current version November 5, 2018. This work was supported in part by Samsung electronics and in part by the Korea Institute for Advancement of Technology grant funded by the Korean government (Ministry of Trade, Industry and Energy, HRD Program for Software-SoC convergence) under Grant N0001883. This paper was recommended by Associate Editor P. K. Meher. (Corresponding author: Jin-Sung Kim.) J. Yum is with the System LSI Division, Samsung Electronics Corporation, Hwaseong 18448, South Korea. Publisher Copyright: {\textcopyright} 1991-2012 IEEE.",

year = "2018",

month = nov,

doi = "10.1109/TCSVT.2017.2740175",

language = "English",

volume = "28",

pages = "3251--3261",

journal = "IEEE Transactions on Circuits and Systems for Video Technology",

issn = "1051-8215",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "11",

}

TY - JOUR

T1 - A Hardware Architecture for the Affine-Invariant Extension of SIFT

AU - Yum, Joohyuk

AU - Lee, Chul Hee

AU - Park, Jinwoo

AU - Kim, Jin Sung

AU - Lee, Hyuk Jae

N1 - Funding Information: Manuscript received November 14, 2016; revised July 11, 2017; accepted July 29, 2017. Date of publication August 15, 2017; date of current version November 5, 2018. This work was supported in part by Samsung electronics and in part by the Korea Institute for Advancement of Technology grant funded by the Korean government (Ministry of Trade, Industry and Energy, HRD Program for Software-SoC convergence) under Grant N0001883. This paper was recommended by Associate Editor P. K. Meher. (Corresponding author: Jin-Sung Kim.) J. Yum is with the System LSI Division, Samsung Electronics Corporation, Hwaseong 18448, South Korea. Publisher Copyright: © 1991-2012 IEEE.

PY - 2018/11

Y1 - 2018/11

N2 - Affine-invariant extension of scale-invariant feature transform (ASIFT) algorithm requires a large amount of computation and memory access, and consequently, is hard to process in real time. In order to increase the operation speed of ASIFT algorithm, this paper proposes a new hardware architecture for the ASIFT algorithm. In order to reduce the memory access time, the affine transform is modified to allow external memory access in the raster-scan order with a little accuracy drop. In addition, image filtering with skewed kernel is proposed in order to reduce the memory space for image storage. Additional complexity reduction is attempted to reduce the number of simulated viewpoints. As a result, throughput of the affine transform module is increased to 325% and the proposed hardware processes a video graphics array-sized (640×480) video at 20 fps.

AB - Affine-invariant extension of scale-invariant feature transform (ASIFT) algorithm requires a large amount of computation and memory access, and consequently, is hard to process in real time. In order to increase the operation speed of ASIFT algorithm, this paper proposes a new hardware architecture for the ASIFT algorithm. In order to reduce the memory access time, the affine transform is modified to allow external memory access in the raster-scan order with a little accuracy drop. In addition, image filtering with skewed kernel is proposed in order to reduce the memory space for image storage. Additional complexity reduction is attempted to reduce the number of simulated viewpoints. As a result, throughput of the affine transform module is increased to 325% and the proposed hardware processes a video graphics array-sized (640×480) video at 20 fps.

UR - http://www.scopus.com/inward/record.url?scp=85028459814&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85028459814&partnerID=8YFLogxK

U2 - 10.1109/TCSVT.2017.2740175

DO - 10.1109/TCSVT.2017.2740175

M3 - Article

AN - SCOPUS:85028459814

SN - 1051-8215

VL - 28

SP - 3251

EP - 3261

JO - IEEE Transactions on Circuits and Systems for Video Technology

JF - IEEE Transactions on Circuits and Systems for Video Technology

IS - 11

M1 - 8010882

ER -

A Hardware Architecture for the Affine-Invariant Extension of SIFT

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