A Giga-b/s CMOS Clock and Data Recovery Circuit with a Novel Adaptive Phase Detector

Jae Wook Lee; Cheon O. Lee; Woo Young Choi

A Giga-b/s CMOS Clock and Data Recovery Circuit with a Novel Adaptive Phase Detector

Jae Wook Lee, Cheon O. Lee, Woo Young Choi

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

A giga-b/s CMOS clock and data recovery circuit with a adaptive phase detector were studied. It was found that high frequency jitter is one of the major performance-limiting factor. It was also found that the phase detector is able to suppress the noise and stable clock generation.

Original language	English
Pages (from-to)	2186-2189
Number of pages	4
Journal	IEICE Transactions on Communications
Volume	E86-B
Issue number	7
Publication status	Published - 2003 Jul

All Science Journal Classification (ASJC) codes

Software
Computer Networks and Communications
Electrical and Electronic Engineering

Cite this

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title = "A Giga-b/s CMOS Clock and Data Recovery Circuit with a Novel Adaptive Phase Detector",

abstract = "A giga-b/s CMOS clock and data recovery circuit with a adaptive phase detector were studied. It was found that high frequency jitter is one of the major performance-limiting factor. It was also found that the phase detector is able to suppress the noise and stable clock generation.",

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A Giga-b/s CMOS Clock and Data Recovery Circuit with a Novel Adaptive Phase Detector

Abstract

All Science Journal Classification (ASJC) codes

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