A fully associative, tagless DRAM cache

Yongjun Lee, Jongwon Kim, Hakbeom Jang, Hyunggyun Yang, Jangwoo Kim, Jinkyu Jeong, Jae W. Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

60 Citations (Scopus)


This paper introduces a tagless cache architecture for large in-package DRAM caches. The conventional die-stacked DRAM cache has both a TLB and a cache tag array, which are responsible for virtual-to-physical and physical-to-cache address translation, respectively. We propose to align the granularity of caching with OS page size and take a unified approach to address translation and cache tag management. To this end, we introduce cache-map TLB (cTLB), which stores virtual-to-cache, instead of virtual-to-physical, address mappings. At a TLB miss, the TLB miss handler allocates the requested block into the cache if it is not cached yet, and updates both the page table and cTLB with the virtual-to-cache address mapping. Assuming the availability of large in-package DRAM caches, this ensures that an access to the memory region within the TLB reach always hits in the cache with low hit latency since a TLB access immediately returns the exact location of the requested block in the cache, hence saving a tag-checking operation. The remaining cache space is used as victim cache for memory pages that are recently evicted from cTLB. By completely eliminating data structures for cache tag management, from either on-die SRAM or in-package DRAM, the proposed DRAM cache achieves best scalability and hit latency, while maintaining high hit rate of a fully associative cache. Our evaluation with 3D Through-Silicon Via (TSV)-based in-package DRAM demonstrates that the proposed cache improves the IPC and energy efficiency by 30.9% and 39.5%, respectively, compared to the baseline with no DRAM cache. These numbers translate to 4.3% and 23.8% improvements over an impractical SRAM-tag cache requiring megabytes of on-die SRAM storage, due to low hit latency and zero energy waste for cache tags.

Original languageEnglish
Title of host publicationISCA 2015 - 42nd Annual International Symposium on Computer Architecture, Conference Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages12
ISBN (Electronic)9781450334020
Publication statusPublished - 2015 Jun 13
Event42nd Annual International Symposium on Computer Architecture, ISCA 2015 - Portland, United States
Duration: 2015 Jun 132015 Jun 17

Publication series

NameProceedings - International Symposium on Computer Architecture
ISSN (Print)1063-6897


Other42nd Annual International Symposium on Computer Architecture, ISCA 2015
Country/TerritoryUnited States

Bibliographical note

Publisher Copyright:
© 2015 ACM.

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture


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