A frequency scaling model for energy efficient DVFS designs based on circuit delay optimization

Ki Bum Chun; Changmin Lee; Won Woo Ro

doi:10.1109/ISCE.2015.7177841

A frequency scaling model for energy efficient DVFS designs based on circuit delay optimization

Ki Bum Chun, Changmin Lee, Won Woo Ro

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

DVFS techniques that have more than one operating mode provide several pairs of operating frequencies and supply voltages. As circuit delays vary with supply voltages, an effort to optimize the circuit delays is necessarily required. The primary impediment to optimize the extra circuits is an increase of power overheads because it prevents satisfying power constraints of the DVFS design. In this paper, we propose an analytic model to find energy efficient points regarding the power overheads induced by the extra circuit costs. The analytic model consists of two parameters: frequency scaling factor and operational duty cycle. In a parameter sweep, optimal frequencies of a low-power mode can be estimated as compared with a high-performance mode.

Original language	English
Title of host publication	2015 International Symposium on Consumer Electronics, ISCE 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781467373654
DOIs	https://doi.org/10.1109/ISCE.2015.7177841
Publication status	Published - 2015 Aug 4
Event	IEEE International Symposium on Consumer Electronics, ISCE 2015 - Madrid, Spain Duration: 2015 Jun 24 → 2015 Jun 26

Publication series

Name	Proceedings of the International Symposium on Consumer Electronics, ISCE
Volume	2015-August

Other

Other	IEEE International Symposium on Consumer Electronics, ISCE 2015
Country/Territory	Spain
City	Madrid
Period	15/6/24 → 15/6/26

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

All Science Journal Classification (ASJC) codes

General Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/ISCE.2015.7177841

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Chun, K. B., Lee, C., & Ro, W. W. (2015). A frequency scaling model for energy efficient DVFS designs based on circuit delay optimization. In 2015 International Symposium on Consumer Electronics, ISCE 2015 Article 7177841 (Proceedings of the International Symposium on Consumer Electronics, ISCE; Vol. 2015-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCE.2015.7177841

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title = "A frequency scaling model for energy efficient DVFS designs based on circuit delay optimization",

abstract = "DVFS techniques that have more than one operating mode provide several pairs of operating frequencies and supply voltages. As circuit delays vary with supply voltages, an effort to optimize the circuit delays is necessarily required. The primary impediment to optimize the extra circuits is an increase of power overheads because it prevents satisfying power constraints of the DVFS design. In this paper, we propose an analytic model to find energy efficient points regarding the power overheads induced by the extra circuit costs. The analytic model consists of two parameters: frequency scaling factor and operational duty cycle. In a parameter sweep, optimal frequencies of a low-power mode can be estimated as compared with a high-performance mode.",

keywords = "DVFS, energy efficiency, frequency scaling factor",

author = "Chun, {Ki Bum} and Changmin Lee and Ro, {Won Woo}",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; IEEE International Symposium on Consumer Electronics, ISCE 2015 ; Conference date: 24-06-2015 Through 26-06-2015",

year = "2015",

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doi = "10.1109/ISCE.2015.7177841",

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Chun, KB, Lee, C & Ro, WW 2015, A frequency scaling model for energy efficient DVFS designs based on circuit delay optimization. in 2015 International Symposium on Consumer Electronics, ISCE 2015., 7177841, Proceedings of the International Symposium on Consumer Electronics, ISCE, vol. 2015-August, Institute of Electrical and Electronics Engineers Inc., IEEE International Symposium on Consumer Electronics, ISCE 2015, Madrid, Spain, 15/6/24. https://doi.org/10.1109/ISCE.2015.7177841

A frequency scaling model for energy efficient DVFS designs based on circuit delay optimization. / Chun, Ki Bum; Lee, Changmin; Ro, Won Woo.
2015 International Symposium on Consumer Electronics, ISCE 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 7177841 (Proceedings of the International Symposium on Consumer Electronics, ISCE; Vol. 2015-August).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A frequency scaling model for energy efficient DVFS designs based on circuit delay optimization

AU - Chun, Ki Bum

AU - Lee, Changmin

AU - Ro, Won Woo

PY - 2015/8/4

Y1 - 2015/8/4

N2 - DVFS techniques that have more than one operating mode provide several pairs of operating frequencies and supply voltages. As circuit delays vary with supply voltages, an effort to optimize the circuit delays is necessarily required. The primary impediment to optimize the extra circuits is an increase of power overheads because it prevents satisfying power constraints of the DVFS design. In this paper, we propose an analytic model to find energy efficient points regarding the power overheads induced by the extra circuit costs. The analytic model consists of two parameters: frequency scaling factor and operational duty cycle. In a parameter sweep, optimal frequencies of a low-power mode can be estimated as compared with a high-performance mode.

AB - DVFS techniques that have more than one operating mode provide several pairs of operating frequencies and supply voltages. As circuit delays vary with supply voltages, an effort to optimize the circuit delays is necessarily required. The primary impediment to optimize the extra circuits is an increase of power overheads because it prevents satisfying power constraints of the DVFS design. In this paper, we propose an analytic model to find energy efficient points regarding the power overheads induced by the extra circuit costs. The analytic model consists of two parameters: frequency scaling factor and operational duty cycle. In a parameter sweep, optimal frequencies of a low-power mode can be estimated as compared with a high-performance mode.

KW - DVFS

KW - energy efficiency

KW - frequency scaling factor

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DO - 10.1109/ISCE.2015.7177841

M3 - Conference contribution

AN - SCOPUS:84953267016

T3 - Proceedings of the International Symposium on Consumer Electronics, ISCE

BT - 2015 International Symposium on Consumer Electronics, ISCE 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE International Symposium on Consumer Electronics, ISCE 2015

Y2 - 24 June 2015 through 26 June 2015

ER -

A frequency scaling model for energy efficient DVFS designs based on circuit delay optimization

Abstract

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UN SDGs

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