DVFS techniques that have more than one operating mode provide several pairs of operating frequencies and supply voltages. As circuit delays vary with supply voltages, an effort to optimize the circuit delays is necessarily required. The primary impediment to optimize the extra circuits is an increase of power overheads because it prevents satisfying power constraints of the DVFS design. In this paper, we propose an analytic model to find energy efficient points regarding the power overheads induced by the extra circuit costs. The analytic model consists of two parameters: frequency scaling factor and operational duty cycle. In a parameter sweep, optimal frequencies of a low-power mode can be estimated as compared with a high-performance mode.
|Title of host publication||2015 International Symposium on Consumer Electronics, ISCE 2015|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Publication status||Published - 2015 Aug 4|
|Event||IEEE International Symposium on Consumer Electronics, ISCE 2015 - Madrid, Spain|
Duration: 2015 Jun 24 → 2015 Jun 26
|Name||Proceedings of the International Symposium on Consumer Electronics, ISCE|
|Other||IEEE International Symposium on Consumer Electronics, ISCE 2015|
|Period||15/6/24 → 15/6/26|
Bibliographical notePublisher Copyright:
© 2015 IEEE.
All Science Journal Classification (ASJC) codes