A floating point divider performing IEEE rounding and quotient conversion in parallel

Woo Chan Park; Tack Don Han; Sung Bong Yang

doi:10.1007/978-3-540-30102-8_47

A floating point divider performing IEEE rounding and quotient conversion in parallel

Woo Chan Park, Tack Don Han, Sung Bong Yang

College of Computing

Research output: Chapter in Book/Report/Conference proceeding › Chapter

1 Citation (Scopus)

Abstract

Processing floating point division generally consists of SRT recurrence, quotient conversion, rounding, and normalization steps. In the rounding step, a high speed adder is required for increment operation, increasing the overall execution time. In this paper, a floating point divider performing quotient conversion and rounding in parallel is presented by analyzing the operational characteristics of floating point division. The proposed floating point divider does not require any additional execution time, nor does it need any high speed adder for the rounding step. The proposed divider can execute quotient conversion, rounding, and normalization within one cycle. To support design efficiency, the quotient conversion/rounding unit of the proposed divider can be shared efficiently with the addition/rounding hardware for floating point multiplier.

Original language	English
Title of host publication	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Editors	Pen-Chung Yew, Jingling Xue
Publisher	Springer Verlag
Pages	568-581
Number of pages	14
ISBN (Electronic)	3540230033, 9783540230038
DOIs	https://doi.org/10.1007/978-3-540-30102-8_47
Publication status	Published - 2004

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	3189
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

All Science Journal Classification (ASJC) codes

Theoretical Computer Science
Computer Science(all)

Access to Document

10.1007/978-3-540-30102-8_47

Cite this

Park, W. C., Han, T. D., & Yang, S. B. (2004). A floating point divider performing IEEE rounding and quotient conversion in parallel. In P-C. Yew, & J. Xue (Eds.), Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (pp. 568-581). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 3189). Springer Verlag. https://doi.org/10.1007/978-3-540-30102-8_47

Park, Woo Chan ; Han, Tack Don ; Yang, Sung Bong. / A floating point divider performing IEEE rounding and quotient conversion in parallel. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). editor / Pen-Chung Yew ; Jingling Xue. Springer Verlag, 2004. pp. 568-581 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

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abstract = "Processing floating point division generally consists of SRT recurrence, quotient conversion, rounding, and normalization steps. In the rounding step, a high speed adder is required for increment operation, increasing the overall execution time. In this paper, a floating point divider performing quotient conversion and rounding in parallel is presented by analyzing the operational characteristics of floating point division. The proposed floating point divider does not require any additional execution time, nor does it need any high speed adder for the rounding step. The proposed divider can execute quotient conversion, rounding, and normalization within one cycle. To support design efficiency, the quotient conversion/rounding unit of the proposed divider can be shared efficiently with the addition/rounding hardware for floating point multiplier.",

author = "Park, {Woo Chan} and Han, {Tack Don} and Yang, {Sung Bong}",

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series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",

publisher = "Springer Verlag",

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Park, WC, Han, TD & Yang, SB 2004, A floating point divider performing IEEE rounding and quotient conversion in parallel. in P-C Yew & J Xue (eds), Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 3189, Springer Verlag, pp. 568-581. https://doi.org/10.1007/978-3-540-30102-8_47

A floating point divider performing IEEE rounding and quotient conversion in parallel. / Park, Woo Chan; Han, Tack Don ; Yang, Sung Bong.
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). ed. / Pen-Chung Yew; Jingling Xue. Springer Verlag, 2004. p. 568-581 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 3189).

Research output: Chapter in Book/Report/Conference proceeding › Chapter

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T1 - A floating point divider performing IEEE rounding and quotient conversion in parallel

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AU - Han, Tack Don

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N2 - Processing floating point division generally consists of SRT recurrence, quotient conversion, rounding, and normalization steps. In the rounding step, a high speed adder is required for increment operation, increasing the overall execution time. In this paper, a floating point divider performing quotient conversion and rounding in parallel is presented by analyzing the operational characteristics of floating point division. The proposed floating point divider does not require any additional execution time, nor does it need any high speed adder for the rounding step. The proposed divider can execute quotient conversion, rounding, and normalization within one cycle. To support design efficiency, the quotient conversion/rounding unit of the proposed divider can be shared efficiently with the addition/rounding hardware for floating point multiplier.

AB - Processing floating point division generally consists of SRT recurrence, quotient conversion, rounding, and normalization steps. In the rounding step, a high speed adder is required for increment operation, increasing the overall execution time. In this paper, a floating point divider performing quotient conversion and rounding in parallel is presented by analyzing the operational characteristics of floating point division. The proposed floating point divider does not require any additional execution time, nor does it need any high speed adder for the rounding step. The proposed divider can execute quotient conversion, rounding, and normalization within one cycle. To support design efficiency, the quotient conversion/rounding unit of the proposed divider can be shared efficiently with the addition/rounding hardware for floating point multiplier.

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Park WC, Han TD , Yang SB. A floating point divider performing IEEE rounding and quotient conversion in parallel. In Yew P-C, Xue J, editors, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Springer Verlag. 2004. p. 568-581. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/978-3-540-30102-8_47

A floating point divider performing IEEE rounding and quotient conversion in parallel

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