A dual-capture wide dynamic range CMOS image sensor using floating-diffusion capacitor

Dongsoo Kim; Youngcheol Chae; Jihyun Cho; Gunhee Han

doi:10.1109/TED.2008.2003023

A dual-capture wide dynamic range CMOS image sensor using floating-diffusion capacitor

Dongsoo Kim, Youngcheol Chae, Jihyun Cho, Gunhee Han

Research output: Contribution to journal › Article › peer-review

21 Citations (Scopus)

Abstract

A dual-capture wide dynamic range CMOS image sensor using an in-pixel floating-diffusion (FD) storage capacitor is proposed. The proposed structure uses the FD as a storage capacitor. The potential of the FD node is read out using a floating-gate capacitor without a contact metallization of the FD node to reduce the leakage. The proposed sensor was fabricated using a 0.35-μm CMOS process. The chip includes 320 × 240 pixels whose pitch is 5.6 μm and whose fill factor is 36%. The measurement results show 100-dB dynamic range, and the leakage at the non-metalized FD is reduced to about one-third of that of the conventional FD with the contact metallization.

Original language	English
Pages (from-to)	2590-2594
Number of pages	5
Journal	IEEE Transactions on Electron Devices
Volume	55
Issue number	10
DOIs	https://doi.org/10.1109/TED.2008.2003023
Publication status	Published - 2008

Bibliographical note

Funding Information:
Manuscript received January 29, 2008; revised May 27, 2008. Current version published September 24, 2008. This work was supported by Sam-sung Electronics Company, Ltd. The review of this paper was arranged by Editor J. Tower.

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/TED.2008.2003023

Cite this

@article{42aa381385c3494eb9ecfc889495ac35,

title = "A dual-capture wide dynamic range CMOS image sensor using floating-diffusion capacitor",

abstract = "A dual-capture wide dynamic range CMOS image sensor using an in-pixel floating-diffusion (FD) storage capacitor is proposed. The proposed structure uses the FD as a storage capacitor. The potential of the FD node is read out using a floating-gate capacitor without a contact metallization of the FD node to reduce the leakage. The proposed sensor was fabricated using a 0.35-μm CMOS process. The chip includes 320 × 240 pixels whose pitch is 5.6 μm and whose fill factor is 36%. The measurement results show 100-dB dynamic range, and the leakage at the non-metalized FD is reduced to about one-third of that of the conventional FD with the contact metallization.",

author = "Dongsoo Kim and Youngcheol Chae and Jihyun Cho and Gunhee Han",

note = "Funding Information: Manuscript received January 29, 2008; revised May 27, 2008. Current version published September 24, 2008. This work was supported by Sam-sung Electronics Company, Ltd. The review of this paper was arranged by Editor J. Tower.",

year = "2008",

doi = "10.1109/TED.2008.2003023",

language = "English",

volume = "55",

pages = "2590--2594",

journal = "IEEE Transactions on Electron Devices",

issn = "0018-9383",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "10",

}

TY - JOUR

T1 - A dual-capture wide dynamic range CMOS image sensor using floating-diffusion capacitor

AU - Kim, Dongsoo

AU - Chae, Youngcheol

AU - Cho, Jihyun

AU - Han, Gunhee

N1 - Funding Information: Manuscript received January 29, 2008; revised May 27, 2008. Current version published September 24, 2008. This work was supported by Sam-sung Electronics Company, Ltd. The review of this paper was arranged by Editor J. Tower.

PY - 2008

Y1 - 2008

N2 - A dual-capture wide dynamic range CMOS image sensor using an in-pixel floating-diffusion (FD) storage capacitor is proposed. The proposed structure uses the FD as a storage capacitor. The potential of the FD node is read out using a floating-gate capacitor without a contact metallization of the FD node to reduce the leakage. The proposed sensor was fabricated using a 0.35-μm CMOS process. The chip includes 320 × 240 pixels whose pitch is 5.6 μm and whose fill factor is 36%. The measurement results show 100-dB dynamic range, and the leakage at the non-metalized FD is reduced to about one-third of that of the conventional FD with the contact metallization.

AB - A dual-capture wide dynamic range CMOS image sensor using an in-pixel floating-diffusion (FD) storage capacitor is proposed. The proposed structure uses the FD as a storage capacitor. The potential of the FD node is read out using a floating-gate capacitor without a contact metallization of the FD node to reduce the leakage. The proposed sensor was fabricated using a 0.35-μm CMOS process. The chip includes 320 × 240 pixels whose pitch is 5.6 μm and whose fill factor is 36%. The measurement results show 100-dB dynamic range, and the leakage at the non-metalized FD is reduced to about one-third of that of the conventional FD with the contact metallization.

UR - http://www.scopus.com/inward/record.url?scp=53649084498&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=53649084498&partnerID=8YFLogxK

U2 - 10.1109/TED.2008.2003023

DO - 10.1109/TED.2008.2003023

M3 - Article

AN - SCOPUS:53649084498

SN - 0018-9383

VL - 55

SP - 2590

EP - 2594

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

IS - 10

ER -

A dual-capture wide dynamic range CMOS image sensor using floating-diffusion capacitor

Abstract

Bibliographical note

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this