A Double-Sensing-Margin Offset-Canceling Dual-Stage Sensing Circuit for Resistive Nonvolatile Memory

Taehui Na; Jisu Kim; Jung Pill Kim; Seung H. Kang; Seong Ook Jung

doi:10.1109/TCSII.2015.2468993

A Double-Sensing-Margin Offset-Canceling Dual-Stage Sensing Circuit for Resistive Nonvolatile Memory

Taehui Na, Jisu Kim, Jung Pill Kim, Seung H. Kang, Seong Ook Jung

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

23 Citations (Scopus)

Abstract

Resistive nonvolatile memory (NVM) devices such as spin transfer torque random access memory (STT-RAM) and resistive random access memory are considered to be leading candidates for next-generation memory devices. With technology scaling, the sensing margin (SM) of the resistive NVM devices is significantly degraded because of increased process variation and decreased read current. In this brief, we propose an offset-canceling dual-stage sensing circuit (OCDS-SC) that has the two major advantages of offset voltage cancelation and double SM. Monte Carlo HSPICE simulation results using a 45-nm technology for STT-RAM show that the OCDS-SC achieves a read access yield of 99.93% for 32 Mb (6.6 sigma) with a read current of 15 μA and sensing time of 3.4 ns.

Original language	English
Article number	7206572
Pages (from-to)	1109-1113
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	62
Issue number	12
DOIs	https://doi.org/10.1109/TCSII.2015.2468993
Publication status	Published - 2015 Dec

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Publisher Copyright:
© 2015 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/TCSII.2015.2468993

Cite this

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abstract = "Resistive nonvolatile memory (NVM) devices such as spin transfer torque random access memory (STT-RAM) and resistive random access memory are considered to be leading candidates for next-generation memory devices. With technology scaling, the sensing margin (SM) of the resistive NVM devices is significantly degraded because of increased process variation and decreased read current. In this brief, we propose an offset-canceling dual-stage sensing circuit (OCDS-SC) that has the two major advantages of offset voltage cancelation and double SM. Monte Carlo HSPICE simulation results using a 45-nm technology for STT-RAM show that the OCDS-SC achieves a read access yield of 99.93% for 32 Mb (6.6 sigma) with a read current of 15 μA and sensing time of 3.4 ns.",

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AU - Jung, Seong Ook

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A Double-Sensing-Margin Offset-Canceling Dual-Stage Sensing Circuit for Resistive Nonvolatile Memory

Abstract

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