In this paper, a delay locked loop (DLL) based clock generator is proposed. In this DLL, a dual edge triggered phase detector (DET-PD) with a high phase detector gain, a wide phase capture range, and a reduced reset time is proposed in order to achieve fast lock speed without degrading the loop stability. To resolve the static phase offset problem of previous DET-PDs, a feedback based duty cycle controller is proposed. A high speed frequency multiplier is also proposed in order to achieve a high operating frequency and a wide operating range. The proposed DET-PD shows a 4.19 ps static phase offset at a typical corner, which is 10.5 times better than that of the conventional DET-PD based DLL, and shows a 2.36 - 2.51 times improved lock speed compared with a single edge triggered phase detector (SET-PD) based DLL. Also, the proposed clock generator achieves an operating range of 150 MHz - 2 GHz and frequency multiplication factor of x1 - x8.
|Number of pages||7|
|Journal||IEEE Transactions on Consumer Electronics|
|Publication status||Published - 2010 Aug|
Bibliographical noteFunding Information:
1This work was supported by the IT R&D program of MKE/KEIT [10034834, a development of ASIC chip for next generation high speed ATE].
All Science Journal Classification (ASJC) codes
- Media Technology
- Electrical and Electronic Engineering