Editor's note: Debug and validation are important steps required to ensure that systems-on-chip satisfies the design specs. This article presents an elegant diagnosis technique integrated within the network-on-chip infrastructure. The authors demonstrate the proposed technique on an FPGA prototype.-Umit Y.
|Number of pages||7|
|Journal||IEEE Design and Test|
|Publication status||Published - 2019 Apr|
Bibliographical noteFunding Information:
This work was supported in part by the ICT R&D Program of MSIT/IITP (2018-0-00197, Development of ultra-low power intelligent edge system-on-chip technology based on lightweight RISC-V processor), and in part by NRF of Korea funded by the Ministry of Education (2017R1D1A1B03027911).
© 2013 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering