A Diagnosable Network-on-Chip for FPGA Verification of Intellectual Properties

Kyuseung Han; Jae Jin Lee; Woojoo Lee; Jinho Lee

doi:10.1109/MDAT.2018.2890238

A Diagnosable Network-on-Chip for FPGA Verification of Intellectual Properties

Kyuseung Han, Jae Jin Lee, Woojoo Lee, Jinho Lee

College of Computing

Research output: Contribution to journal › Article › peer-review

3 Citations (Scopus)

Abstract

Editor's note: Debug and validation are important steps required to ensure that systems-on-chip satisfies the design specs. This article presents an elegant diagnosis technique integrated within the network-on-chip infrastructure. The authors demonstrate the proposed technique on an FPGA prototype.-Umit Y.

Original language	English
Article number	8594625
Pages (from-to)	81-87
Number of pages	7
Journal	IEEE Design and Test
Volume	36
Issue number	2
DOIs	https://doi.org/10.1109/MDAT.2018.2890238
Publication status	Published - 2019 Apr

Bibliographical note

Funding Information:
This work was supported in part by the ICT R&D Program of MSIT/IITP (2018-0-00197, Development of ultra-low power intelligent edge system-on-chip technology based on lightweight RISC-V processor), and in part by NRF of Korea funded by the Ministry of Education (2017R1D1A1B03027911).

Publisher Copyright:
© 2013 IEEE.

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/MDAT.2018.2890238

Cite this

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abstract = "Editor's note: Debug and validation are important steps required to ensure that systems-on-chip satisfies the design specs. This article presents an elegant diagnosis technique integrated within the network-on-chip infrastructure. The authors demonstrate the proposed technique on an FPGA prototype.-Umit Y.",

author = "Kyuseung Han and Lee, {Jae Jin} and Woojoo Lee and Jinho Lee",

note = "Funding Information: This work was supported in part by the ICT R&D Program of MSIT/IITP (2018-0-00197, Development of ultra-low power intelligent edge system-on-chip technology based on lightweight RISC-V processor), and in part by NRF of Korea funded by the Ministry of Education (2017R1D1A1B03027911). Publisher Copyright: {\textcopyright} 2013 IEEE.",

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AU - Lee, Jinho

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A Diagnosable Network-on-Chip for FPGA Verification of Intellectual Properties

Abstract

Bibliographical note

All Science Journal Classification (ASJC) codes

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