This research is to design a low power set-associative cache for embedded processors without additional delay or performance degradation. For this goal, deterministic way selection logic with power-aware replacement policy is designed to enable only one way of set-associative cache as in the direct-mapped cache. Delay analysis shows that the cache access time is almost the same as that of conventional set associative cache with additional way selection logic. Proposed architecture exploits the trade-offs between power and performance to achieve power reduction with the least performance loss. As the result of those approaches, simulation shows that the proposed architecture can reduce unit accessing power consumption by 59% over conventional set-associative caches with average 0.06% of negligible performance loss.
|Number of pages||7|
|Journal||Microprocessors and Microsystems|
|Publication status||Published - 2006 Jun 6|
Bibliographical noteFunding Information:
This work was supported by Samsung Co. “Design of adaptive parallel accelerator and DSP/SIMD hybrid system for high performance media applications” project.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Computer Networks and Communications
- Artificial Intelligence