Abstract
We present a high-speed power-efficient fast searcher module for an initial code acquisition in CDMA wireless local loop (WLL) system. We introduce a double-dwell serial search algorithm with 16 parallel active correlators to meet mean code acquisition time required in WLL system. We pipeline parallel active correlators and make use of a common energy processing element and a microcontroller I/F block. As a result, hardware complexity is reduced to only 1/4 of a conventional searcher consisting of 16 correlators.
| Original language | English |
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| Title of host publication | ICVC 1999 - 6th International Conference on VLSI and CAD |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 582-585 |
| Number of pages | 4 |
| ISBN (Print) | 0780357272, 9780780357273 |
| DOIs | |
| Publication status | Published - 1999 |
| Event | 6th International Conference on VLSI and CAD, ICVC 1999 - Seoul, Korea, Republic of Duration: 1999 Oct 26 → 1999 Oct 27 |
Publication series
| Name | ICVC 1999 - 6th International Conference on VLSI and CAD |
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Other
| Other | 6th International Conference on VLSI and CAD, ICVC 1999 |
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| Country/Territory | Korea, Republic of |
| City | Seoul |
| Period | 99/10/26 → 99/10/27 |
Bibliographical note
Funding Information:This study was supported by the academic research fund of Ministry of Education, Republic of Korea, through Inter-University Semiconductor Research Center (ISRC 97-E-2039) in Seoul National University
Publisher Copyright:
© 1999 IEEE.
All Science Journal Classification (ASJC) codes
- Computer Graphics and Computer-Aided Design
- Hardware and Architecture
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials