A debug scheme to improve the error identification in post-silicon validation

Inhyuk Choi, Won Jung, Hyunggoy Oh, Sungho Kang

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)


While developing semiconductors, post-silicon validation is an important step to identify the errors that are not detected during the pre-silicon verification and manufacturing testing phases. When the design complexity increases, the required debug time also increases because additional debug data are required to identify the errors. In this study, we present a debug scheme that improves the error identification capability. The proposed debug approach concurrently generates three types of signatures using hierarchical multiple-input signature registers (MISRs). The error-suspect debug cycles are determined by analyzing the debug cycles that are commonly contained in the erroneous signatures of the three MISRs. To reduce the amount of debug data, we compare the high-level MISR signatures in real time with the golden signatures; further, we handle the remaining two MISRs based on the tag bits that are obtained from the results of the high-level MISR. The experimental results prove that the proposed debug structure can significantly improve the error identification capability using less debug data than that used in previous debug structure.

Original languageEnglish
Article numbere0202216
JournalPloS one
Issue number9
Publication statusPublished - 2018 Sept

Bibliographical note

Publisher Copyright:
© 2018 Choi et al. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.

All Science Journal Classification (ASJC) codes

  • General Biochemistry,Genetics and Molecular Biology
  • General Agricultural and Biological Sciences
  • General


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