A dataflow-centric approach to design low power control paths in CGRAs

Hyunchul Park; Yongjun Park; Scott Mahlke

doi:10.1109/SASP.2009.5226330

A dataflow-centric approach to design low power control paths in CGRAs

Hyunchul Park, Yongjun Park, Scott Mahlke

College of Computing

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing high computation throughput, scalability, low cost, and energy efficiency, but suffer from relatively high control path power consumption. We take the concept of a token network from dataflow machines and apply it to the control path of CGRAs to increase efficiency. As a result, instruction memory power is reduced by 74%, the overall control path power by 56%, andthe total system power by 25%.

Original language	English
Title of host publication	2009 IEEE 7th Symposium on Application Specific Processors, SASP 2009
Pages	15-20
Number of pages	6
DOIs	https://doi.org/10.1109/SASP.2009.5226330
Publication status	Published - 2009
Event	2009 IEEE 7th Symposium on Application Specific Processors, SASP 2009 - San Francisco, CA, United States Duration: 2009 Jul 27 → 2009 Jul 28

Publication series

Name	2009 IEEE 7th Symposium on Application Specific Processors, SASP 2009

Conference

Conference	2009 IEEE 7th Symposium on Application Specific Processors, SASP 2009
Country/Territory	United States
City	San Francisco, CA
Period	09/7/27 → 09/7/28

All Science Journal Classification (ASJC) codes

Computer Science Applications
Hardware and Architecture

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/SASP.2009.5226330

Cite this

@inproceedings{91cab1443cf74b09985e3a033427b84d,

title = "A dataflow-centric approach to design low power control paths in CGRAs",

abstract = "Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing high computation throughput, scalability, low cost, and energy efficiency, but suffer from relatively high control path power consumption. We take the concept of a token network from dataflow machines and apply it to the control path of CGRAs to increase efficiency. As a result, instruction memory power is reduced by 74%, the overall control path power by 56%, andthe total system power by 25%.",

author = "Hyunchul Park and Yongjun Park and Scott Mahlke",

year = "2009",

doi = "10.1109/SASP.2009.5226330",

language = "English",

isbn = "9781424449385",

series = "2009 IEEE 7th Symposium on Application Specific Processors, SASP 2009",

pages = "15--20",

booktitle = "2009 IEEE 7th Symposium on Application Specific Processors, SASP 2009",

note = "2009 IEEE 7th Symposium on Application Specific Processors, SASP 2009 ; Conference date: 27-07-2009 Through 28-07-2009",

}

Park, H, Park, Y & Mahlke, S 2009, A dataflow-centric approach to design low power control paths in CGRAs. in 2009 IEEE 7th Symposium on Application Specific Processors, SASP 2009., 5226330, 2009 IEEE 7th Symposium on Application Specific Processors, SASP 2009, pp. 15-20, 2009 IEEE 7th Symposium on Application Specific Processors, SASP 2009, San Francisco, CA, United States, 09/7/27. https://doi.org/10.1109/SASP.2009.5226330

A dataflow-centric approach to design low power control paths in CGRAs. / Park, Hyunchul; Park, Yongjun; Mahlke, Scott.
2009 IEEE 7th Symposium on Application Specific Processors, SASP 2009. 2009. p. 15-20 5226330 (2009 IEEE 7th Symposium on Application Specific Processors, SASP 2009).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A dataflow-centric approach to design low power control paths in CGRAs

AU - Park, Hyunchul

AU - Park, Yongjun

AU - Mahlke, Scott

PY - 2009

Y1 - 2009

N2 - Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing high computation throughput, scalability, low cost, and energy efficiency, but suffer from relatively high control path power consumption. We take the concept of a token network from dataflow machines and apply it to the control path of CGRAs to increase efficiency. As a result, instruction memory power is reduced by 74%, the overall control path power by 56%, andthe total system power by 25%.

AB - Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing high computation throughput, scalability, low cost, and energy efficiency, but suffer from relatively high control path power consumption. We take the concept of a token network from dataflow machines and apply it to the control path of CGRAs to increase efficiency. As a result, instruction memory power is reduced by 74%, the overall control path power by 56%, andthe total system power by 25%.

UR - http://www.scopus.com/inward/record.url?scp=70350746334&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=70350746334&partnerID=8YFLogxK

U2 - 10.1109/SASP.2009.5226330

DO - 10.1109/SASP.2009.5226330

M3 - Conference contribution

AN - SCOPUS:70350746334

SN - 9781424449385

T3 - 2009 IEEE 7th Symposium on Application Specific Processors, SASP 2009

SP - 15

EP - 20

BT - 2009 IEEE 7th Symposium on Application Specific Processors, SASP 2009

T2 - 2009 IEEE 7th Symposium on Application Specific Processors, SASP 2009

Y2 - 27 July 2009 through 28 July 2009

ER -

A dataflow-centric approach to design low power control paths in CGRAs

Abstract

Publication series

Conference

All Science Journal Classification (ASJC) codes

UN SDGs

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