A comprehensive model for low frequency noise in poly-Si thin-film transistors

This paper presents a comprehensive model for 1/f noise in poly-Si thin-film transistors in the linear regime where the current is controlled by the gate bias with a small fixed drain bias. For small gate biases the conduction and noise generation is dominated by thermionic emission at the grain boundary where as for large gate biases the conduction and noise generation is dominated by drift in the grain bulk region. The generation of the 1/f noise in the grain bulk can explained by the 'Unified Model' for crystalline Si-MOSFET's. However, the noise from grain boundary should be explained by number fluctuation models such as thermal activation model via barrier height modulation. An expression for the critical barrier height or gate bias, which severs these two regimes, is derived.