Abstract
In this paper, we propose a new clustered reconfigurable interconnect network (CRIN) BIST that can improve the embedding probabilities of random-pattern-resistant-patterns. A simulated annealing based algorithm that maximizes the embedding probabilities of scan test cubes has been developed to reorder scan cells. Experimental results demonstrate that the proposed CRIN BIST technique reduces test time by 35% and the storage requirement by 39% in comparison with previous work.
Original language | English |
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Pages (from-to) | 354-357 |
Number of pages | 4 |
Journal | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |
Volume | E89-A |
Issue number | 1 |
DOIs | |
Publication status | Published - 2006 Jan |
All Science Journal Classification (ASJC) codes
- Signal Processing
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering
- Applied Mathematics