TY - JOUR
T1 - A Case for In-Memory Random Scatter-Gather for Fast Graph Processing
AU - Shin, Changmin
AU - Kwon, Taehee
AU - Song, Jaeyong
AU - Ju, Jae Hyung
AU - Liu, Frank
AU - Choi, Yeonkyu
AU - Lee, Jinho
N1 - Publisher Copyright:
© 2002-2011 IEEE.
PY - 2024/1/1
Y1 - 2024/1/1
N2 - Because of the widely recognized memory wall issue, modern DRAMs are increasingly being assigned innovative functionalities beyond the basic read and write operations. Often referred to as 'function-in-memory', these techniques are crafted to leverage the abundant internal bandwidth available within the DRAM. However, these techniques face several challenges, including requiring large areas for arithmetic units and the necessity of splitting a single word into multiple pieces. These challenges severely limit the practical application of these function-in-memory techniques. In this paper, we present Piccolo, an efficient design of random scatter-gather memory. Our method achieves significant improvements with minimal overhead. By demonstrating our technique on a graph processing accelerator, we show that Piccolo and the proposed accelerator achieves 1.2-3.1 ×1.2-3.1× speedup compared to the prior art.
AB - Because of the widely recognized memory wall issue, modern DRAMs are increasingly being assigned innovative functionalities beyond the basic read and write operations. Often referred to as 'function-in-memory', these techniques are crafted to leverage the abundant internal bandwidth available within the DRAM. However, these techniques face several challenges, including requiring large areas for arithmetic units and the necessity of splitting a single word into multiple pieces. These challenges severely limit the practical application of these function-in-memory techniques. In this paper, we present Piccolo, an efficient design of random scatter-gather memory. Our method achieves significant improvements with minimal overhead. By demonstrating our technique on a graph processing accelerator, we show that Piccolo and the proposed accelerator achieves 1.2-3.1 ×1.2-3.1× speedup compared to the prior art.
KW - Accelerator architectures
KW - in-memory computing
KW - memory architecture
KW - parallel processing
KW - random access memory
UR - http://www.scopus.com/inward/record.url?scp=85187996795&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85187996795&partnerID=8YFLogxK
U2 - 10.1109/LCA.2024.3376680
DO - 10.1109/LCA.2024.3376680
M3 - Article
AN - SCOPUS:85187996795
SN - 1556-6056
VL - 23
SP - 73
EP - 77
JO - IEEE Computer Architecture Letters
JF - IEEE Computer Architecture Letters
IS - 1
ER -