A BIRA using fault-free memory region for area reduction

As memory capacity and density grow, the test cost and yield improvement of embedded memories have become more crucial. For embedded memories, BIRA (built-in redundancy analysis) is widely used to improve yield. BIRA replaces faulty cells with spare cells. BIRA requires an extra hardware overhead since it needs to store and analyze faults. The most important factor in BIRA is the reduction of area overhead while keeping very high repair rate. Most of previous studies on BIRA utilize CAMs (content-addressable memories) for storing faulty memory addresses. The area overhead for CAM is not negligible, hence, a CAM is shared by many memory blocks to perform a repair process. With this BIRA architecture, each memory block needs to be analyzed one by one. This makes the CAM a bottleneck of improvement for area overhead and analysis speed in BIRA. In order to improve area overhead and analysis speed, we propose a BIRA architecture and RA (redundancy analysis) algorithm using a fault-free region in embedded memory instead of deploying extra CAMs. The proposed RA algorithm stores faulty cell addresses in the fault-free region and achieves a very high repair rate. The proposed BIRA brings a significant area reduction. In addition, it allows a parallel memory test by using its own memory instead of shared CAMs.