A 990-μW 1.6-GHz PLL based on a novel supply-regulated active-loop-filter VCO

Kwang Chun Choi; Sung Geun Kim; Seung Woo Lee; Bhum Cheol Lee; Woo Young Choi

doi:10.1109/TCSII.2013.2258253

A 990-μW 1.6-GHz PLL based on a novel supply-regulated active-loop-filter VCO

Kwang Chun Choi, Sung Geun Kim, Seung Woo Lee, Bhum Cheol Lee, Woo Young Choi

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

15 Citations (Scopus)

Abstract

A low-power 1.6-GHz phase-locked loop (PLL) based on a novel supply-regulated voltage-controlled oscillator (SR-VCO) including an active-loop filter (ALF) is realized. In this PLL, an active $RC$ filter is combined with SR-VCO, achieving the advantages of ALF PLL without penalties in power consumption or phase noises. The PLL has measured rms jitter of 4.82 ps, and its core consumes 990 μW from 1-V supply while the chip area is 420 × 570μm² including on-chip passive components required for the ALF and the supply regulator.

Original language	English
Article number	6518184
Pages (from-to)	311-315
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	60
Issue number	6
DOIs	https://doi.org/10.1109/TCSII.2013.2258253
Publication status	Published - 2013

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/TCSII.2013.2258253

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title = "A 990-μW 1.6-GHz PLL based on a novel supply-regulated active-loop-filter VCO",

abstract = "A low-power 1.6-GHz phase-locked loop (PLL) based on a novel supply-regulated voltage-controlled oscillator (SR-VCO) including an active-loop filter (ALF) is realized. In this PLL, an active $RC$ filter is combined with SR-VCO, achieving the advantages of ALF PLL without penalties in power consumption or phase noises. The PLL has measured rms jitter of 4.82 ps, and its core consumes 990 μW from 1-V supply while the chip area is 420 × 570μm2 including on-chip passive components required for the ALF and the supply regulator.",

author = "Choi, {Kwang Chun} and Kim, {Sung Geun} and Lee, {Seung Woo} and Lee, {Bhum Cheol} and Choi, {Woo Young}",

year = "2013",

doi = "10.1109/TCSII.2013.2258253",

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AU - Choi, Kwang Chun

AU - Kim, Sung Geun

AU - Lee, Seung Woo

AU - Lee, Bhum Cheol

AU - Choi, Woo Young

PY - 2013

Y1 - 2013

N2 - A low-power 1.6-GHz phase-locked loop (PLL) based on a novel supply-regulated voltage-controlled oscillator (SR-VCO) including an active-loop filter (ALF) is realized. In this PLL, an active $RC$ filter is combined with SR-VCO, achieving the advantages of ALF PLL without penalties in power consumption or phase noises. The PLL has measured rms jitter of 4.82 ps, and its core consumes 990 μW from 1-V supply while the chip area is 420 × 570μm2 including on-chip passive components required for the ALF and the supply regulator.

AB - A low-power 1.6-GHz phase-locked loop (PLL) based on a novel supply-regulated voltage-controlled oscillator (SR-VCO) including an active-loop filter (ALF) is realized. In this PLL, an active $RC$ filter is combined with SR-VCO, achieving the advantages of ALF PLL without penalties in power consumption or phase noises. The PLL has measured rms jitter of 4.82 ps, and its core consumes 990 μW from 1-V supply while the chip area is 420 × 570μm2 including on-chip passive components required for the ALF and the supply regulator.

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A 990-μW 1.6-GHz PLL based on a novel supply-regulated active-loop-filter VCO

Abstract

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