A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system

C. H. Kim; J. H. Lee; J. B. Lee; B. S. Kim; C. S. Park; S. B. Lee; S. Y. Lee; C. W. Park; J. G. Roh; H. S. Nam; D. G. Kim; D. Y. Lee; T. S. Jung; H. Yoon; S. I. Cho

doi:10.1109/4.726563

A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system

C. H. Kim, J. H. Lee, J. B. Lee, B. S. Kim, C. S. Park, S. B. Lee, S. Y. Lee, C. W. Park, J. G. Roh, H. S. Nam, D. G. Kim, D. Y. Lee, T. S. Jung, H. Yoon, S. I. Cho

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

22 Citations (Scopus)

Abstract

A 64-Mbit bidirectional data strobed, double-data-rate SDRAM achieves a peak bandwidth of 2.56 GByte/s on a 64-bit-channel, 256-MByte memory system at V_cc = 3.3 V and T = 25°C. The circuit features are: 1) a bidirectional data strobing scheme to eliminate the clock-related skews of I/O data in a multimodule system, 2) a low-power delay-locked loop having a wide range of locking frequency (40-160 MHz) with fast access time and minimal variations, and 3) a twisted data bussing architecture with minimized loading difference between I/O data paths and small chip-size overhead associated with the 2-bit prefetch operation.

Original language	English
Pages (from-to)	1703-1709
Number of pages	7
Journal	IEEE Journal of Solid-State Circuits
Volume	33
Issue number	11
DOIs	https://doi.org/10.1109/4.726563
Publication status	Published - 1998 Nov

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/4.726563

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Kim, C. H., Lee, J. H., Lee, J. B., Kim, B. S., Park, C. S., Lee, S. B., Lee, S. Y., Park, C. W., Roh, J. G., Nam, H. S., Kim, D. G., Lee, D. Y., Jung, T. S., Yoon, H., & Cho, S. I. (1998). A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system. IEEE Journal of Solid-State Circuits, 33(11), 1703-1709. https://doi.org/10.1109/4.726563

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title = "A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system",

abstract = "A 64-Mbit bidirectional data strobed, double-data-rate SDRAM achieves a peak bandwidth of 2.56 GByte/s on a 64-bit-channel, 256-MByte memory system at Vcc = 3.3 V and T = 25°C. The circuit features are: 1) a bidirectional data strobing scheme to eliminate the clock-related skews of I/O data in a multimodule system, 2) a low-power delay-locked loop having a wide range of locking frequency (40-160 MHz) with fast access time and minimal variations, and 3) a twisted data bussing architecture with minimized loading difference between I/O data paths and small chip-size overhead associated with the 2-bit prefetch operation.",

author = "Kim, {C. H.} and Lee, {J. H.} and Lee, {J. B.} and Kim, {B. S.} and Park, {C. S.} and Lee, {S. B.} and Lee, {S. Y.} and Park, {C. W.} and Roh, {J. G.} and Nam, {H. S.} and Kim, {D. G.} and Lee, {D. Y.} and Jung, {T. S.} and H. Yoon and Cho, {S. I.}",

year = "1998",

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language = "English",

volume = "33",

pages = "1703--1709",

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Kim, CH, Lee, JH, Lee, JB, Kim, BS, Park, CS, Lee, SB, Lee, SY, Park, CW, Roh, JG, Nam, HS, Kim, DG, Lee, DY, Jung, TS, Yoon, H & Cho, SI 1998, 'A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system', IEEE Journal of Solid-State Circuits, vol. 33, no. 11, pp. 1703-1709. https://doi.org/10.1109/4.726563

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AU - Lee, J. H.

AU - Lee, J. B.

AU - Kim, B. S.

AU - Park, C. S.

AU - Lee, S. B.

AU - Lee, S. Y.

AU - Park, C. W.

AU - Roh, J. G.

AU - Nam, H. S.

AU - Kim, D. G.

AU - Lee, D. Y.

AU - Jung, T. S.

AU - Yoon, H.

AU - Cho, S. I.

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AB - A 64-Mbit bidirectional data strobed, double-data-rate SDRAM achieves a peak bandwidth of 2.56 GByte/s on a 64-bit-channel, 256-MByte memory system at Vcc = 3.3 V and T = 25°C. The circuit features are: 1) a bidirectional data strobing scheme to eliminate the clock-related skews of I/O data in a multimodule system, 2) a low-power delay-locked loop having a wide range of locking frequency (40-160 MHz) with fast access time and minimal variations, and 3) a twisted data bussing architecture with minimized loading difference between I/O data paths and small chip-size overhead associated with the 2-bit prefetch operation.

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A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system

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