A 622-Mb/s mixed-mode BPSK demodulator using a half-rate bang-bang phase detector

Duho Kim; Kwang Chun Choi; Young Kwang Seo; Hyunchin Kim; Woo Young Choi

doi:10.1109/JSSC.2008.2004327

A 622-Mb/s mixed-mode BPSK demodulator using a half-rate bang-bang phase detector

Duho Kim, Kwang Chun Choi, Young Kwang Seo, Hyunchin Kim, Woo Young Choi

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

9 Citations (Scopus)

Abstract

A new mixed-mode binary phase shift keying (BFSK) demodulator is demonstrated using a half-rate bang-bang phase detector commonly used in clock and data recovery (CDR) applications. This demodulator can be used for new home networking applications using already installed CATV lines. A prototype chip realized by 0.18-μm CMOS process can demodulate 622-Mb/s data at 1.4-GHz carrier frequency. At this data rate, the demodulator core consumes 27.5 mW from a 1.8 V power supply while the core chip area is 210 × 150 μm ². The transmission over 20-m CATV line using the prototype chip is successfully demonstrated.

Original language	English
Article number	4639541
Pages (from-to)	2284-2292
Number of pages	9
Journal	IEEE Journal of Solid-State Circuits
Volume	43
Issue number	10
DOIs	https://doi.org/10.1109/JSSC.2008.2004327
Publication status	Published - 2008 Oct

Bibliographical note

Funding Information:
Manuscript received August 11, 2007; revised June 17, 2008. Current version published October 8, 2008. This work was supported by “System IC 2010” project of Korea Ministry of Knowledge Economy and the IC Design Education Center (IDEC), Korea, and by Digital Solution Center of CTO, Samsung Electronics Co. Ltd.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/JSSC.2008.2004327

Cite this

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title = "A 622-Mb/s mixed-mode BPSK demodulator using a half-rate bang-bang phase detector",

abstract = "A new mixed-mode binary phase shift keying (BFSK) demodulator is demonstrated using a half-rate bang-bang phase detector commonly used in clock and data recovery (CDR) applications. This demodulator can be used for new home networking applications using already installed CATV lines. A prototype chip realized by 0.18-μm CMOS process can demodulate 622-Mb/s data at 1.4-GHz carrier frequency. At this data rate, the demodulator core consumes 27.5 mW from a 1.8 V power supply while the core chip area is 210 × 150 μm 2. The transmission over 20-m CATV line using the prototype chip is successfully demonstrated.",

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AU - Choi, Woo Young

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A 622-Mb/s mixed-mode BPSK demodulator using a half-rate bang-bang phase detector

Abstract

Bibliographical note

All Science Journal Classification (ASJC) codes

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