A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock over 20 dB Loss Channel

Kwanseoauth Park; Jinhyungauth Lee; Kwanghoauth Lee; Min Seongauth Choo; Sungchunauth Jang; Sang Hyeokauth Chu; Sungwooauth Kim; Deog Kyoon Jeong

doi:10.1109/TCSII.2017.2747148

A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock over 20 dB Loss Channel

Kwanseoauth Park, Jinhyungauth Lee, Kwanghoauth Lee, Min Seongauth Choo, Sungchunauth Jang, Sang Hyeokauth Chu, Sungwooauth Kim, Deog Kyoon Jeong

School of System & Semiconductor Engineering

Research output: Contribution to journal › Article › peer-review

4 Citations (Scopus)

Abstract

A 1.62-to-8.1 Gb/s video interface receiver with an adaptive equalizer and a stream clock generator (SCG) is proposed. The adaptation logic is achieved by an edge-based adaptation and it controls the continuous-time linear equalizer ac boost. Using the adaptation logic, the minimum BER point is selected for several cables. The SCG consists of a phase-switching fractional divider and a delta-sigma modulator. The dividing factor is determined by the display resolution and the SCG operates up to 680 MHz which is the 4K UHD pixel frequency. The proposed receiver is fabricated in 65-nm CMOS technology and occupies an active area of 0.282 mm². The measured BER is less than $10^{-12}$ with a 20-ft-long video cable, whose insertion loss at 4.05 GHz is 20 dB. The receiver consumes 55.1 mW at the data rate of 8.1 Gb/s.

Original language	English
Article number	8022928
Pages (from-to)	1432-1436
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	64
Issue number	12
DOIs	https://doi.org/10.1109/TCSII.2017.2747148
Publication status	Published - 2017 Dec

Bibliographical note

Publisher Copyright:
© 2004-2012 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/TCSII.2017.2747148

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@article{548d2a39ca604c63b667bd083a04f6d1,

title = "A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock over 20 dB Loss Channel",

abstract = "A 1.62-to-8.1 Gb/s video interface receiver with an adaptive equalizer and a stream clock generator (SCG) is proposed. The adaptation logic is achieved by an edge-based adaptation and it controls the continuous-time linear equalizer ac boost. Using the adaptation logic, the minimum BER point is selected for several cables. The SCG consists of a phase-switching fractional divider and a delta-sigma modulator. The dividing factor is determined by the display resolution and the SCG operates up to 680 MHz which is the 4K UHD pixel frequency. The proposed receiver is fabricated in 65-nm CMOS technology and occupies an active area of 0.282 mm2. The measured BER is less than $10^{-12}$ with a 20-ft-long video cable, whose insertion loss at 4.05 GHz is 20 dB. The receiver consumes 55.1 mW at the data rate of 8.1 Gb/s.",

author = "Kwanseoauth Park and Jinhyungauth Lee and Kwanghoauth Lee and Choo, {Min Seongauth} and Sungchunauth Jang and Chu, {Sang Hyeokauth} and Sungwooauth Kim and Jeong, {Deog Kyoon}",

note = "Publisher Copyright: {\textcopyright} 2004-2012 IEEE.",

year = "2017",

month = dec,

doi = "10.1109/TCSII.2017.2747148",

language = "English",

volume = "64",

pages = "1432--1436",

journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",

issn = "1549-7747",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "12",

}

TY - JOUR

T1 - A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock over 20 dB Loss Channel

AU - Park, Kwanseoauth

AU - Lee, Jinhyungauth

AU - Lee, Kwanghoauth

AU - Choo, Min Seongauth

AU - Jang, Sungchunauth

AU - Chu, Sang Hyeokauth

AU - Kim, Sungwooauth

AU - Jeong, Deog Kyoon

PY - 2017/12

Y1 - 2017/12

N2 - A 1.62-to-8.1 Gb/s video interface receiver with an adaptive equalizer and a stream clock generator (SCG) is proposed. The adaptation logic is achieved by an edge-based adaptation and it controls the continuous-time linear equalizer ac boost. Using the adaptation logic, the minimum BER point is selected for several cables. The SCG consists of a phase-switching fractional divider and a delta-sigma modulator. The dividing factor is determined by the display resolution and the SCG operates up to 680 MHz which is the 4K UHD pixel frequency. The proposed receiver is fabricated in 65-nm CMOS technology and occupies an active area of 0.282 mm2. The measured BER is less than $10^{-12}$ with a 20-ft-long video cable, whose insertion loss at 4.05 GHz is 20 dB. The receiver consumes 55.1 mW at the data rate of 8.1 Gb/s.

AB - A 1.62-to-8.1 Gb/s video interface receiver with an adaptive equalizer and a stream clock generator (SCG) is proposed. The adaptation logic is achieved by an edge-based adaptation and it controls the continuous-time linear equalizer ac boost. Using the adaptation logic, the minimum BER point is selected for several cables. The SCG consists of a phase-switching fractional divider and a delta-sigma modulator. The dividing factor is determined by the display resolution and the SCG operates up to 680 MHz which is the 4K UHD pixel frequency. The proposed receiver is fabricated in 65-nm CMOS technology and occupies an active area of 0.282 mm2. The measured BER is less than $10^{-12}$ with a 20-ft-long video cable, whose insertion loss at 4.05 GHz is 20 dB. The receiver consumes 55.1 mW at the data rate of 8.1 Gb/s.

UR - http://www.scopus.com/inward/record.url?scp=85028731395&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85028731395&partnerID=8YFLogxK

U2 - 10.1109/TCSII.2017.2747148

DO - 10.1109/TCSII.2017.2747148

M3 - Article

AN - SCOPUS:85028731395

SN - 1549-7747

VL - 64

SP - 1432

EP - 1436

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

IS - 12

M1 - 8022928

ER -

A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock over 20 dB Loss Channel

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