A 5.4Gb/s adaptive equalizer using asynchronous-sampling histograms

As the data rate requirements for many wireline applications increase, channel bandwidth limitation becomes a critical problem in serial interfaces. Equalizers are often used as a solution for this problem. In addition, many applications require the equalizer to be adaptive so that it can provide optimized equalization for different channel conditions. Various types of adaptive equalizers have been investigated for high-speed serial interface applications [1-6]. In the spectrum-balancing method, adaptive equalization is achieved by comparing high and low frequency components of signal power and generating feedback signals until the power spectrum is balanced [1]. Unfortunately, the precision of this scheme is easily affected by process variations, and capacitors both in filters and the feedback loop occupy a large Si area. Digital-signal processing based on maximum likelihood sequence detection can be used for adaptive equalization [2]. But, speed limitation and architecture complexity of ADC limits applicability of this scheme in high-speed applications. In the eye-opening monitoring (EOM) scheme, quality of the signal eye diagram is measured and used for equalizer adaptation [3-6]. For this method, a clock-recovery circuit is needed in order to generate clock signals synchronized to data for sampling. However, it can be difficult to recover clock signals from the initially closed eye diagram, limiting the applicability of this scheme. In this paper, we demonstrate an adaptive equalizer based on asynchronous-sampling histograms.