TY - GEN
T1 - A 5.2-mW, 2.5-Gb/s limiting amplifer for OC-48 SONET applications
AU - Yoo, Kwisung
AU - Han, Gunhee
AU - Park, Sung Min
PY - 2006
Y1 - 2006
N2 - In this paper, a fully differential CMOS limiting amplifier is presented for OC-48 SONET applications. With negative resistance and capacitance characteristics, it achieves significant gain and bandwidth enhancement. The amplifier was implemented in a 0.18-μm CMOS process, occupying the chip area of 0.025mm2. Post-layout simulation results demonstrate the bandwidth of 2.4-GHz, the differential gain of 41-dB, the input sensitivity of 1.5mV pp, and the power consumption of only 5.2mW from a single 1.2-V power supply.
AB - In this paper, a fully differential CMOS limiting amplifier is presented for OC-48 SONET applications. With negative resistance and capacitance characteristics, it achieves significant gain and bandwidth enhancement. The amplifier was implemented in a 0.18-μm CMOS process, occupying the chip area of 0.025mm2. Post-layout simulation results demonstrate the bandwidth of 2.4-GHz, the differential gain of 41-dB, the input sensitivity of 1.5mV pp, and the power consumption of only 5.2mW from a single 1.2-V power supply.
UR - http://www.scopus.com/inward/record.url?scp=47349119889&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=47349119889&partnerID=8YFLogxK
U2 - 10.1109/ICECS.2006.379844
DO - 10.1109/ICECS.2006.379844
M3 - Conference contribution
AN - SCOPUS:47349119889
SN - 1424403952
SN - 9781424403950
T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
SP - 537
EP - 540
BT - ICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems
T2 - ICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems
Y2 - 10 December 2006 through 13 December 2006
ER -