A 5.2-Mpixel 88.4-dB DR 12-in CMOS X-Ray Detector with 16-bit Column-Parallel Continuous-Time Incremental ΔΣ ADCs

Sangwoo Lee, Jinwoong Jeong, Taewoong Kim, Chanmin Park, Taewoo Kim, Youngcheol Chae

Research output: Contribution to journalArticlepeer-review

11 Citations (Scopus)

Abstract

This article presents a 5.2-Mpixel, 12-in wafer-scale CMOS X-ray detector that consists of lithographically stitched 169 sub-chips. The detector employs a 3T pixel with a voltage-controlled storage capacitor to achieve both a low dark random noise (RN) and a large well capacity, and the pixel outputs are read out by column-parallel continuous-time (CT) incremental delta-sigma ( Delta Sigma ) analog-to-digital converters (ADCs). The use of a CT incremental Delta Sigma ADC enables high resolution and low energy consumption while securing uniformity and robustness over the 12-in wafer. This work is fabricated in a 1P4M 65-nm CMOS technology. The 16-bit ADC implemented within a 45- mu text{m} pitch achieves a differential nonlinearity (DNL) of +0.79/-0.65 LSB, an integral nonlinearity (INL) of +6.85/-6.15 LSB, and a peak signal-to-noise ratio (SNR) of 88.5 dB with a conversion time of 12.6mu text{s}. This detector achieves a CFPN of 181mu text {V}_{text {rms}} , a dark RN of 267mu text {V}_{text {rms}} , and a DR of 88.4 dB while consuming 3.9 W at 30 frames/s. Compared with the state of the arts, this work achieves 3times larger spatial resolution, 1.8times higher pixel rate, 1.9times higher energy-efficiency, and 17 dB higher DR, simultaneously.

Original languageEnglish
Article number9162454
Pages (from-to)2878-2888
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume55
Issue number11
DOIs
Publication statusPublished - 2020 Nov

Bibliographical note

Publisher Copyright:
© 1966-2012 IEEE.

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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