A 5.1ms Low-Latency Face Detection Imager with In-Memory Charge-Domain Computing of Machine-Learning Classifiers

Hyunsoo Song, Sungjin Oh, Juan Salinas, Sung Yun Park, Euisik Yoon

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

We present a CMOS imager for low-latency face detection empowered by parallel imaging and computing of machine-learning (ML) classifiers. The energy-efficient parallel operation and multi-scale detection eliminate image capture delay and significantly alleviate backend computational loads. The proposed pixel architecture, composed of dynamic samplers in a global shutter (GS) pixel array, allows for energy-efficient in-memory charge-domain computing of feature extraction and classification. The illumination-invariant detection was realized by using log-Haar features. A prototype 240×240 imager achieved an on-chip face detection latency of 5.1ms with a 97.9% true positive rate and 2% false positive rate at 120fps. Moreover, a dynamic nature of in-memory computing allows an energy efficiency of 419pJ/pixel for feature extraction and classification, leading to the smallest latency-energy product of 3.66msnJ/pixel with digital backend processing.

Original languageEnglish
Title of host publication2021 Symposium on VLSI Circuits, VLSI Circuits 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9784863487796
DOIs
Publication statusPublished - 2021 Jun 13
Event35th Symposium on VLSI Circuits, VLSI Circuits 2021 - Virutal, Online
Duration: 2021 Jun 132021 Jun 19

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume2021-June

Conference

Conference35th Symposium on VLSI Circuits, VLSI Circuits 2021
CityVirutal, Online
Period21/6/1321/6/19

Bibliographical note

Publisher Copyright:
© 2021 JSAP.

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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