A 50 MS/s 65 dB-SNDR Pipelined SAR ADC using Capacitively Degenerated Two-Stage Dynamic Amplifier

Hyunchul Yoon, Teawoong Kim, Yigi Kwon, Youngcheol Chae

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

This paper presents a capacitively degenerated two-stage dynamic amplifier that achieves high voltage gain and good linearity in a residue amplifier of a pipelined SAR ADC. It uses an open-loop dynamic amplifier that exploits a capacitive degeneration, and its limited voltage gain is improved to 16× by using a two-stage configuration. Since the optimal timing of the voltage gain to achieve high linearity can be set with a simple timing generator, the error due to incomplete settling of the residue amplifier can be maintained with negligible power overhead. Fabricated in a 65-nm CMOS process, the pipelined SAR ADC achieves 65-dB SNDR and 79.8-dB SFDR at a sampling rate of 50 MS/s, while consuming only 0.46 mW. This corresponds to a Walden FoM of 6.33 fJ/conv.-step and a Schreier FoM of 172.35 dB.

Original languageEnglish
Title of host publication2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages88-89
Number of pages2
ISBN (Electronic)9781665497725
DOIs
Publication statusPublished - 2022
Event2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 - Honolulu, United States
Duration: 2022 Jun 122022 Jun 17

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
Volume2022-June
ISSN (Print)0743-1562

Conference

Conference2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
Country/TerritoryUnited States
CityHonolulu
Period22/6/1222/6/17

Bibliographical note

Publisher Copyright:
© 2022 IEEE.

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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