TY - JOUR
T1 - A 5 Gb/s Time-Interleaved Voltage-Mode Duobinary Encoding Scheme for 3-D-Stacked IC
AU - Kim, Ji Young
AU - Lee, Jongsoo
AU - Kim, Kiryong
AU - Joo, Sunghwan
AU - Moon, Byoung Mo
AU - Sohn, Kyomin
AU - Jung, Seong Ook
N1 - Publisher Copyright:
© 2022 Institute of Electrical and Electronics Engineers Inc.. All rights reserved.
PY - 2022/6/1
Y1 - 2022/6/1
N2 - A time-interleaved duobinary encoding scheme for the low-power high-bandwidth memory (HBM) I/O interface is proposed with a 65-nm CMOS process. To reduce power consumption in HBM I/O using multiple through-silicon via (TSV) I/Os, a transmitter (TX) that performs duobinary signaling with a voltage-mode driver is proposed. A small area encoder is implemented to generate duobinary output and an edge-boosted pre-driver is proposed to improve the slew rate and the robustness against the process, voltage, and temperature (PVT) variations of the duobinary voltage-mode driver. To convert the duobinary signal into a non-return-to-zero (NRZ) signal, a one-tap decision feedback equalizer (DFE) is used at the receiver (RX). NRZ signal conversion is proposed using one reference voltage and one PMOS switch to reduce the hardware complexity caused by additional reference voltages. An eight-stacked TSV is emulated in the 65-nm CMOS process, and the emulated capacitance of each stack is 100 fF. The energy efficiency of the proposed transceiver chip is 0.373 pJ/b/pF with a 27- 1 pseudorandom binary sequence at 5 Gb/s.
AB - A time-interleaved duobinary encoding scheme for the low-power high-bandwidth memory (HBM) I/O interface is proposed with a 65-nm CMOS process. To reduce power consumption in HBM I/O using multiple through-silicon via (TSV) I/Os, a transmitter (TX) that performs duobinary signaling with a voltage-mode driver is proposed. A small area encoder is implemented to generate duobinary output and an edge-boosted pre-driver is proposed to improve the slew rate and the robustness against the process, voltage, and temperature (PVT) variations of the duobinary voltage-mode driver. To convert the duobinary signal into a non-return-to-zero (NRZ) signal, a one-tap decision feedback equalizer (DFE) is used at the receiver (RX). NRZ signal conversion is proposed using one reference voltage and one PMOS switch to reduce the hardware complexity caused by additional reference voltages. An eight-stacked TSV is emulated in the 65-nm CMOS process, and the emulated capacitance of each stack is 100 fF. The energy efficiency of the proposed transceiver chip is 0.373 pJ/b/pF with a 27- 1 pseudorandom binary sequence at 5 Gb/s.
KW - Duobinary
KW - high-bandwidth memory (HBM) interface
KW - low power memory interface
KW - low-swing single-ended I/O
KW - through-silicon via (TSV)
UR - http://www.scopus.com/inward/record.url?scp=85126268044&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85126268044&partnerID=8YFLogxK
U2 - 10.1109/JSSC.2022.3153666
DO - 10.1109/JSSC.2022.3153666
M3 - Article
AN - SCOPUS:85126268044
SN - 0018-9200
VL - 57
SP - 1913
EP - 1923
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 6
ER -
