A 5 Gb/s Time-Interleaved Voltage-Mode Duobinary Encoding Scheme for 3-D-Stacked IC

Ji Young Kim, Jongsoo Lee, Kiryong Kim, Sunghwan Joo, Byoung Mo Moon, Kyomin Sohn, Seong Ook Jung

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)

Abstract

A time-interleaved duobinary encoding scheme for the low-power high-bandwidth memory (HBM) I/O interface is proposed with a 65-nm CMOS process. To reduce power consumption in HBM I/O using multiple through-silicon via (TSV) I/Os, a transmitter (TX) that performs duobinary signaling with a voltage-mode driver is proposed. A small area encoder is implemented to generate duobinary output and an edge-boosted pre-driver is proposed to improve the slew rate and the robustness against the process, voltage, and temperature (PVT) variations of the duobinary voltage-mode driver. To convert the duobinary signal into a non-return-to-zero (NRZ) signal, a one-tap decision feedback equalizer (DFE) is used at the receiver (RX). NRZ signal conversion is proposed using one reference voltage and one PMOS switch to reduce the hardware complexity caused by additional reference voltages. An eight-stacked TSV is emulated in the 65-nm CMOS process, and the emulated capacitance of each stack is 100 fF. The energy efficiency of the proposed transceiver chip is 0.373 pJ/b/pF with a 27- 1 pseudorandom binary sequence at 5 Gb/s.

Original languageEnglish
Pages (from-to)1913-1923
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume57
Issue number6
DOIs
Publication statusPublished - 2022 Jun 1

Bibliographical note

Publisher Copyright:
© 2022 Institute of Electrical and Electronics Engineers Inc.. All rights reserved.

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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