A 41μW 16MS/s 99.2dB-SFDR Capacitively Degenerated Dynamic Amplifier with Nonlinear-Slope-Factor Compensation

Yunhong Kim; Sungsik Park; Seungwoo Song; Sangwoo Lee; Moonhyung Jang; Changuk Lee; Youngcheol Chae

doi:10.1109/ISSCC19947.2020.9062982

A 41μW 16MS/s 99.2dB-SFDR Capacitively Degenerated Dynamic Amplifier with Nonlinear-Slope-Factor Compensation

Yunhong Kim, Sungsik Park, Seungwoo Song, Sangwoo Lee, Moonhyung Jang, Changuk Lee, Youngcheol Chae

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

The amplifiers used to improve the noise performance in analog front-ends and ADCs must have sufficiently low noise and high linearity to achieve overall system performance targets. Achieving the target noise level requires a certain amount of power, but nonlinearity can be improved by analog or digital techniques. Residue amplifiers used in pipelined ADCs have been improved to dissipate low power, preserving their linearity. Traditionally, closed-loop amplifiers with high open loop-gain are used for the residue amplifiers [1], but they require static current, thus degrading power efficiency. To improve the power efficiency of the residue amplifier, dynamic amplifiers have been investigated [2], [4], which allow using only the required bandwidth, thus minimizing the power consumption for a given noise requirement. However, a dynamic amplifier requires digital calibration to compensate for the nonlinearity, increasing the design complexity and limiting the robustness to PVT variations [2], [3].

Original language	English
Title of host publication	2020 IEEE International Solid-State Circuits Conference, ISSCC 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	358-360
Number of pages	3
ISBN (Electronic)	9781728132044
DOIs	https://doi.org/10.1109/ISSCC19947.2020.9062982
Publication status	Published - 2020 Feb
Event	2020 IEEE International Solid-State Circuits Conference, ISSCC 2020 - San Francisco, United States Duration: 2020 Feb 16 → 2020 Feb 20

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	2020-February
ISSN (Print)	0193-6530

Conference

Conference	2020 IEEE International Solid-State Circuits Conference, ISSCC 2020
Country/Territory	United States
City	San Francisco
Period	20/2/16 → 20/2/20

Bibliographical note

Funding Information:
This work is supported by the Future Interconnect Technology Cluster Program of Samsung Electronics.

Publisher Copyright:
© 2020 IEEE.

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/ISSCC19947.2020.9062982

Cite this

Kim, Y., Park, S., Song, S., Lee, S., Jang, M., Lee, C., & Chae, Y. (2020). A 41μW 16MS/s 99.2dB-SFDR Capacitively Degenerated Dynamic Amplifier with Nonlinear-Slope-Factor Compensation. In 2020 IEEE International Solid-State Circuits Conference, ISSCC 2020 (pp. 358-360). [9062982] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 2020-February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC19947.2020.9062982

Kim, Yunhong ; Park, Sungsik ; Song, Seungwoo et al. / A 41μW 16MS/s 99.2dB-SFDR Capacitively Degenerated Dynamic Amplifier with Nonlinear-Slope-Factor Compensation. 2020 IEEE International Solid-State Circuits Conference, ISSCC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. pp. 358-360 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

@inproceedings{e2c03730e7f144af818a8b5df9519d1d,

title = "A 41μW 16MS/s 99.2dB-SFDR Capacitively Degenerated Dynamic Amplifier with Nonlinear-Slope-Factor Compensation",

abstract = "The amplifiers used to improve the noise performance in analog front-ends and ADCs must have sufficiently low noise and high linearity to achieve overall system performance targets. Achieving the target noise level requires a certain amount of power, but nonlinearity can be improved by analog or digital techniques. Residue amplifiers used in pipelined ADCs have been improved to dissipate low power, preserving their linearity. Traditionally, closed-loop amplifiers with high open loop-gain are used for the residue amplifiers [1], but they require static current, thus degrading power efficiency. To improve the power efficiency of the residue amplifier, dynamic amplifiers have been investigated [2], [4], which allow using only the required bandwidth, thus minimizing the power consumption for a given noise requirement. However, a dynamic amplifier requires digital calibration to compensate for the nonlinearity, increasing the design complexity and limiting the robustness to PVT variations [2], [3].",

author = "Yunhong Kim and Sungsik Park and Seungwoo Song and Sangwoo Lee and Moonhyung Jang and Changuk Lee and Youngcheol Chae",

note = "Funding Information: This work is supported by the Future Interconnect Technology Cluster Program of Samsung Electronics. Publisher Copyright: {\textcopyright} 2020 IEEE.; 2020 IEEE International Solid-State Circuits Conference, ISSCC 2020 ; Conference date: 16-02-2020 Through 20-02-2020",

year = "2020",

month = feb,

doi = "10.1109/ISSCC19947.2020.9062982",

language = "English",

series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "358--360",

booktitle = "2020 IEEE International Solid-State Circuits Conference, ISSCC 2020",

address = "United States",

}

Kim, Y, Park, S, Song, S, Lee, S, Jang, M, Lee, C & Chae, Y 2020, A 41μW 16MS/s 99.2dB-SFDR Capacitively Degenerated Dynamic Amplifier with Nonlinear-Slope-Factor Compensation. in 2020 IEEE International Solid-State Circuits Conference, ISSCC 2020., 9062982, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 2020-February, Institute of Electrical and Electronics Engineers Inc., pp. 358-360, 2020 IEEE International Solid-State Circuits Conference, ISSCC 2020, San Francisco, United States, 20/2/16. https://doi.org/10.1109/ISSCC19947.2020.9062982

A 41μW 16MS/s 99.2dB-SFDR Capacitively Degenerated Dynamic Amplifier with Nonlinear-Slope-Factor Compensation. / Kim, Yunhong; Park, Sungsik; Song, Seungwoo et al.
2020 IEEE International Solid-State Circuits Conference, ISSCC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 358-360 9062982 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 2020-February).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A 41μW 16MS/s 99.2dB-SFDR Capacitively Degenerated Dynamic Amplifier with Nonlinear-Slope-Factor Compensation

AU - Kim, Yunhong

AU - Park, Sungsik

AU - Song, Seungwoo

AU - Lee, Sangwoo

AU - Jang, Moonhyung

AU - Lee, Changuk

AU - Chae, Youngcheol

PY - 2020/2

Y1 - 2020/2

N2 - The amplifiers used to improve the noise performance in analog front-ends and ADCs must have sufficiently low noise and high linearity to achieve overall system performance targets. Achieving the target noise level requires a certain amount of power, but nonlinearity can be improved by analog or digital techniques. Residue amplifiers used in pipelined ADCs have been improved to dissipate low power, preserving their linearity. Traditionally, closed-loop amplifiers with high open loop-gain are used for the residue amplifiers [1], but they require static current, thus degrading power efficiency. To improve the power efficiency of the residue amplifier, dynamic amplifiers have been investigated [2], [4], which allow using only the required bandwidth, thus minimizing the power consumption for a given noise requirement. However, a dynamic amplifier requires digital calibration to compensate for the nonlinearity, increasing the design complexity and limiting the robustness to PVT variations [2], [3].

AB - The amplifiers used to improve the noise performance in analog front-ends and ADCs must have sufficiently low noise and high linearity to achieve overall system performance targets. Achieving the target noise level requires a certain amount of power, but nonlinearity can be improved by analog or digital techniques. Residue amplifiers used in pipelined ADCs have been improved to dissipate low power, preserving their linearity. Traditionally, closed-loop amplifiers with high open loop-gain are used for the residue amplifiers [1], but they require static current, thus degrading power efficiency. To improve the power efficiency of the residue amplifier, dynamic amplifiers have been investigated [2], [4], which allow using only the required bandwidth, thus minimizing the power consumption for a given noise requirement. However, a dynamic amplifier requires digital calibration to compensate for the nonlinearity, increasing the design complexity and limiting the robustness to PVT variations [2], [3].

UR - http://www.scopus.com/inward/record.url?scp=85083864769&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85083864769&partnerID=8YFLogxK

U2 - 10.1109/ISSCC19947.2020.9062982

DO - 10.1109/ISSCC19947.2020.9062982

M3 - Conference contribution

AN - SCOPUS:85083864769

T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

SP - 358

EP - 360

BT - 2020 IEEE International Solid-State Circuits Conference, ISSCC 2020

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2020 IEEE International Solid-State Circuits Conference, ISSCC 2020

Y2 - 16 February 2020 through 20 February 2020

ER -

Kim Y, Park S, Song S, Lee S, Jang M, Lee C et al. A 41μW 16MS/s 99.2dB-SFDR Capacitively Degenerated Dynamic Amplifier with Nonlinear-Slope-Factor Compensation. In 2020 IEEE International Solid-State Circuits Conference, ISSCC 2020. Institute of Electrical and Electronics Engineers Inc. 2020. p. 358-360. 9062982. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC19947.2020.9062982

A 41μW 16MS/s 99.2dB-SFDR Capacitively Degenerated Dynamic Amplifier with Nonlinear-Slope-Factor Compensation

Abstract

Publication series

Conference

Bibliographical note

All Science Journal Classification (ASJC) codes

Access to Document

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