A 3.5/7.0/14-Gb/s multi-rate clock and data recovery circuit with a multi-mode rotational binary phase detector

Ki Hyun Pyun; Dae Hyun Kwon; Woo Young Choi

doi:10.1109/APCCAS.2016.7803966

A 3.5/7.0/14-Gb/s multi-rate clock and data recovery circuit with a multi-mode rotational binary phase detector

Ki Hyun Pyun, Dae Hyun Kwon, Woo Young Choi

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

A new type of multi-rate clock and data recovery (CDR) circuit is realized that can operate at multiple data rates of 3.5, 7.0 and 14-Gb/s. A multi-mode rotational binary phase detector supports full-rate, half-rate and quarter-rate CDR operation with only one voltage-controlled oscillator. A prototype CDR circuit implemented in 65nm CMOS technology successfully demonstrates the multi-rate operation with energy efficiency of 0.64pJ/bit and chip size of 0.017mm², both of which are much less than those of conventional multi-rate CDR circuits.

Original language	English
Title of host publication	2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	327-329
Number of pages	3
ISBN (Electronic)	9781509015702
DOIs	https://doi.org/10.1109/APCCAS.2016.7803966
Publication status	Published - 2017 Jan 3
Event	2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 - Jeju, Korea, Republic of Duration: 2016 Oct 25 → 2016 Oct 28

Publication series

Name	2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016

Other

Other	2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
Country/Territory	Korea, Republic of
City	Jeju
Period	16/10/25 → 16/10/28

Bibliographical note

Funding Information:
This work was supported in by the National Research Foundation of Korea [MEST 2015R1A2A2A01007772] and Samsung Electronics. The authors are also thankful to IDEC for MPW and EDA software support

Publisher Copyright:
© 2016 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Signal Processing

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/APCCAS.2016.7803966

Cite this

Pyun, K. H., Kwon, D. H., & Choi, W. Y. (2017). A 3.5/7.0/14-Gb/s multi-rate clock and data recovery circuit with a multi-mode rotational binary phase detector. In 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 (pp. 327-329). Article 7803966 (2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2016.7803966

Pyun, Ki Hyun ; Kwon, Dae Hyun ; Choi, Woo Young. / A 3.5/7.0/14-Gb/s multi-rate clock and data recovery circuit with a multi-mode rotational binary phase detector. 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 327-329 (2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016).

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abstract = "A new type of multi-rate clock and data recovery (CDR) circuit is realized that can operate at multiple data rates of 3.5, 7.0 and 14-Gb/s. A multi-mode rotational binary phase detector supports full-rate, half-rate and quarter-rate CDR operation with only one voltage-controlled oscillator. A prototype CDR circuit implemented in 65nm CMOS technology successfully demonstrates the multi-rate operation with energy efficiency of 0.64pJ/bit and chip size of 0.017mm2, both of which are much less than those of conventional multi-rate CDR circuits.",

author = "Pyun, {Ki Hyun} and Kwon, {Dae Hyun} and Choi, {Woo Young}",

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Pyun, KH, Kwon, DH & Choi, WY 2017, A 3.5/7.0/14-Gb/s multi-rate clock and data recovery circuit with a multi-mode rotational binary phase detector. in 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016., 7803966, 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016, Institute of Electrical and Electronics Engineers Inc., pp. 327-329, 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016, Jeju, Korea, Republic of, 16/10/25. https://doi.org/10.1109/APCCAS.2016.7803966

A 3.5/7.0/14-Gb/s multi-rate clock and data recovery circuit with a multi-mode rotational binary phase detector. / Pyun, Ki Hyun; Kwon, Dae Hyun; Choi, Woo Young.
2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc., 2017. p. 327-329 7803966 (2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N1 - Funding Information: This work was supported in by the National Research Foundation of Korea [MEST 2015R1A2A2A01007772] and Samsung Electronics. The authors are also thankful to IDEC for MPW and EDA software support Publisher Copyright: © 2016 IEEE.

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AB - A new type of multi-rate clock and data recovery (CDR) circuit is realized that can operate at multiple data rates of 3.5, 7.0 and 14-Gb/s. A multi-mode rotational binary phase detector supports full-rate, half-rate and quarter-rate CDR operation with only one voltage-controlled oscillator. A prototype CDR circuit implemented in 65nm CMOS technology successfully demonstrates the multi-rate operation with energy efficiency of 0.64pJ/bit and chip size of 0.017mm2, both of which are much less than those of conventional multi-rate CDR circuits.

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Pyun KH, Kwon DH, Choi WY. A 3.5/7.0/14-Gb/s multi-rate clock and data recovery circuit with a multi-mode rotational binary phase detector. In 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc. 2017. p. 327-329. 7803966. (2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016). doi: 10.1109/APCCAS.2016.7803966

A 3.5/7.0/14-Gb/s multi-rate clock and data recovery circuit with a multi-mode rotational binary phase detector

Abstract

Publication series

Other

Bibliographical note

All Science Journal Classification (ASJC) codes

UN SDGs

Access to Document

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