A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit With an Input Slew-Rate Tolerant Selective Transition Detector

Dae Hyun Kwon; Minkyu Kim; Sung Geun Kim; Woo Young Choi

doi:10.1109/TCSII.2018.2855692

A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit With an Input Slew-Rate Tolerant Selective Transition Detector

Dae Hyun Kwon, Minkyu Kim, Sung Geun Kim, Woo Young Choi

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

9 Citations (Scopus)

Abstract

We present a 32-Gb/s PAM-4 quarter-rate clock and data recovery (CDR) circuit having a newly proposed selective transition detector (STD). The STD allows phase detection of PAM-4 data in a simple manner by eliminating middle transition and majority voting with simple logic gates. In addition, using the edge-rotating technique with quarter-rate CDR operation, our CDR achieves power consumption and chip area reduction. A prototype 32-Gb/s quarter-rate PAM-4 CDR circuit is realized with 28-nm CMOS technology. The CDR circuit consumes 32 mW with 1.2-V supply and the recovered clock signal has 0.0136-UI rms jitter.

Original language	English
Article number	8410680
Pages (from-to)	362-366
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	66
Issue number	3
DOIs	https://doi.org/10.1109/TCSII.2018.2855692
Publication status	Published - 2019 Mar

Bibliographical note

Funding Information:
Manuscript received March 28, 2018; revised June 11, 2018; accepted July 4, 2018. Date of publication July 13, 2018; date of current version February 26, 2019. This work was supported by Samsung Electronics; Materials and Parts Technology Research Development Program funded by the Korean Ministry of Trade, Industry and Energy under Project 10065666; Graduate School of Yonsei University Research Scholarship Grants. This brief was recommended by Associate Editor G. Torfs. (Corresponding author: Woo-Young Choi.) The authors are with the High-Speed Circuits and Systems Laboratory, Department of Electrical and Electronic Engineering, Yonsei University, Seoul 120-749, South Korea (e-mail: wchoi@yonsei.ac.kr).

Funding Information:
This work was supported by Samsung Electronics; Materials and Parts Technology Research Development Program funded by the Korean Ministry of Trade, Industry and Energy under Project 10065666; Graduate School of Yonsei University Research Scholarship Grants.

Publisher Copyright:
© 2004-2012 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/TCSII.2018.2855692

Cite this

@article{2673ae3de9fa4fd6bc6ed1372430828e,

title = "A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit With an Input Slew-Rate Tolerant Selective Transition Detector",

abstract = "We present a 32-Gb/s PAM-4 quarter-rate clock and data recovery (CDR) circuit having a newly proposed selective transition detector (STD). The STD allows phase detection of PAM-4 data in a simple manner by eliminating middle transition and majority voting with simple logic gates. In addition, using the edge-rotating technique with quarter-rate CDR operation, our CDR achieves power consumption and chip area reduction. A prototype 32-Gb/s quarter-rate PAM-4 CDR circuit is realized with 28-nm CMOS technology. The CDR circuit consumes 32 mW with 1.2-V supply and the recovered clock signal has 0.0136-UI rms jitter.",

author = "Kwon, {Dae Hyun} and Minkyu Kim and Kim, {Sung Geun} and Choi, {Woo Young}",

note = "Funding Information: Manuscript received March 28, 2018; revised June 11, 2018; accepted July 4, 2018. Date of publication July 13, 2018; date of current version February 26, 2019. This work was supported by Samsung Electronics; Materials and Parts Technology Research Development Program funded by the Korean Ministry of Trade, Industry and Energy under Project 10065666; Graduate School of Yonsei University Research Scholarship Grants. This brief was recommended by Associate Editor G. Torfs. (Corresponding author: Woo-Young Choi.) The authors are with the High-Speed Circuits and Systems Laboratory, Department of Electrical and Electronic Engineering, Yonsei University, Seoul 120-749, South Korea (e-mail: wchoi@yonsei.ac.kr). Funding Information: This work was supported by Samsung Electronics; Materials and Parts Technology Research Development Program funded by the Korean Ministry of Trade, Industry and Energy under Project 10065666; Graduate School of Yonsei University Research Scholarship Grants. Publisher Copyright: {\textcopyright} 2004-2012 IEEE.",

year = "2019",

month = mar,

doi = "10.1109/TCSII.2018.2855692",

language = "English",

volume = "66",

pages = "362--366",

journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",

issn = "1549-7747",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "3",

}

TY - JOUR

T1 - A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit With an Input Slew-Rate Tolerant Selective Transition Detector

AU - Kwon, Dae Hyun

AU - Kim, Minkyu

AU - Kim, Sung Geun

AU - Choi, Woo Young

N1 - Funding Information: Manuscript received March 28, 2018; revised June 11, 2018; accepted July 4, 2018. Date of publication July 13, 2018; date of current version February 26, 2019. This work was supported by Samsung Electronics; Materials and Parts Technology Research Development Program funded by the Korean Ministry of Trade, Industry and Energy under Project 10065666; Graduate School of Yonsei University Research Scholarship Grants. This brief was recommended by Associate Editor G. Torfs. (Corresponding author: Woo-Young Choi.) The authors are with the High-Speed Circuits and Systems Laboratory, Department of Electrical and Electronic Engineering, Yonsei University, Seoul 120-749, South Korea (e-mail: wchoi@yonsei.ac.kr). Funding Information: This work was supported by Samsung Electronics; Materials and Parts Technology Research Development Program funded by the Korean Ministry of Trade, Industry and Energy under Project 10065666; Graduate School of Yonsei University Research Scholarship Grants. Publisher Copyright: © 2004-2012 IEEE.

PY - 2019/3

Y1 - 2019/3

N2 - We present a 32-Gb/s PAM-4 quarter-rate clock and data recovery (CDR) circuit having a newly proposed selective transition detector (STD). The STD allows phase detection of PAM-4 data in a simple manner by eliminating middle transition and majority voting with simple logic gates. In addition, using the edge-rotating technique with quarter-rate CDR operation, our CDR achieves power consumption and chip area reduction. A prototype 32-Gb/s quarter-rate PAM-4 CDR circuit is realized with 28-nm CMOS technology. The CDR circuit consumes 32 mW with 1.2-V supply and the recovered clock signal has 0.0136-UI rms jitter.

AB - We present a 32-Gb/s PAM-4 quarter-rate clock and data recovery (CDR) circuit having a newly proposed selective transition detector (STD). The STD allows phase detection of PAM-4 data in a simple manner by eliminating middle transition and majority voting with simple logic gates. In addition, using the edge-rotating technique with quarter-rate CDR operation, our CDR achieves power consumption and chip area reduction. A prototype 32-Gb/s quarter-rate PAM-4 CDR circuit is realized with 28-nm CMOS technology. The CDR circuit consumes 32 mW with 1.2-V supply and the recovered clock signal has 0.0136-UI rms jitter.

UR - http://www.scopus.com/inward/record.url?scp=85049943252&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85049943252&partnerID=8YFLogxK

U2 - 10.1109/TCSII.2018.2855692

DO - 10.1109/TCSII.2018.2855692

M3 - Article

AN - SCOPUS:85049943252

SN - 1549-7747

VL - 66

SP - 362

EP - 366

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

IS - 3

M1 - 8410680

ER -

A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit With an Input Slew-Rate Tolerant Selective Transition Detector

Abstract

Bibliographical note

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this