A 32-bit carry lookahead adder using dual-path All-N logic

Ge Yang; Seong Ook Jung; Kwang Hyun Baek; Soo Hwan Kim; Suki Kim; Sung Mo Kang

doi:10.1109/TVLSI.2005.853605

A 32-bit carry lookahead adder using dual-path All-N logic

Ge Yang, Seong Ook Jung, Kwang Hyun Baek, Soo Hwan Kim, Suki Kim, Sung Mo Kang

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

15 Citations (Scopus)

Abstract

We have developed dual path all-N logic (DPANL) and applied it to 32-bit adder design for higher performance. The speed is significantly enhanced due to reduced capacitance at each evaluation node of dynamic circuits. The power saving is achieved due to reduced adder cell size and minimal race problem. Post-layout simulation results show that this adder can operate at frequencies up to 1.85 GHz for 0.35-μm 1P4M CMOS technology and is 32.4% faster than the adder using all-N transistor (ANT). It also consumes 29.2% less power than the ANT adder. A 0.35-μm CMOS chip has been fabricated and tested to verify the functionality and performance of the DPANL adder on silicon.

Original language	English
Pages (from-to)	992-996
Number of pages	5
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	13
Issue number	8
DOIs	https://doi.org/10.1109/TVLSI.2005.853605
Publication status	Published - 2005 Aug

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/TVLSI.2005.853605

Cite this

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abstract = "We have developed dual path all-N logic (DPANL) and applied it to 32-bit adder design for higher performance. The speed is significantly enhanced due to reduced capacitance at each evaluation node of dynamic circuits. The power saving is achieved due to reduced adder cell size and minimal race problem. Post-layout simulation results show that this adder can operate at frequencies up to 1.85 GHz for 0.35-μm 1P4M CMOS technology and is 32.4% faster than the adder using all-N transistor (ANT). It also consumes 29.2% less power than the ANT adder. A 0.35-μm CMOS chip has been fabricated and tested to verify the functionality and performance of the DPANL adder on silicon.",

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AU - Kang, Sung Mo

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A 32-bit carry lookahead adder using dual-path All-N logic

Abstract

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