A 3-D Rotation-Based Through-Silicon via Redundancy Architecture for Clustering Faults

Minho Cheong; Ingeol Lee; Sungho Kang

doi:10.1109/TCAD.2019.2927485

A 3-D Rotation-Based Through-Silicon via Redundancy Architecture for Clustering Faults

Minho Cheong, Ingeol Lee, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

6 Citations (Scopus)

Abstract

Three-dimensional integrated circuits (3-D ICs), which feature many benefits, such as high bandwidth and a high degree of integration, have recently received considerable attention from the semiconductor industry. However, these chips feature through-silicon vias (TSVs), which vertically connect multiple dies, and these TSVs may fail, resulting in a decreased yield. Unfortunately, previously proposed methods to repair TSVs cannot handle certain failure patterns. For example, existing techniques cannot repair clustered TSV faults, which commonly occur in practice. Furthermore, the number of signal TSVs typically determines the number of redundant TSVs, which may result in wasteful and redundant TSVs. In this paper, a new TSV repair scheme is proposed that replaces defective TSVs with redundant TSVs by utilizing the architecture of a cube, which can replace any face with any of the other faces. Both signal TSVs and redundant TSVs are placed in the face of cube, so any faulted TSVs can be replaced with redundant TSVs. The experimental results indicate that the new method guarantees 100% coverage with any number of signal TSVs and redundant TSVs.

Original language	English
Article number	8758140
Pages (from-to)	1925-1934
Number of pages	10
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	39
Issue number	9
DOIs	https://doi.org/10.1109/TCAD.2019.2927485
Publication status	Published - 2020 Sept

Bibliographical note

Funding Information:
Manuscript received September 21, 2018; revised January 27, 2019 and May 22, 2019; accepted June 26, 2019. Date of publication July 9, 2019; date of current version August 20, 2020. This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea Government (MSIT) under Grant 2019R1A2C3011079. This paper was recommended by Associate Editor X. Li. (Corresponding author: Sungho Kang.) The authors are with the Computer System and Reliable SOC Laboratory, Department of Electrical and Electronic Engineering, Yonsei University, Seoul 03722, South Korea (e-mail: cmh9292@soc.yonsei.ac.kr; keor@soc.yonsei.ac.kr; shkang@yonsei.ac.kr). Digital Object Identifier 10.1109/TCAD.2019.2927485

Publisher Copyright:
© 1982-2012 IEEE.

All Science Journal Classification (ASJC) codes

Software
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

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10.1109/TCAD.2019.2927485

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abstract = "Three-dimensional integrated circuits (3-D ICs), which feature many benefits, such as high bandwidth and a high degree of integration, have recently received considerable attention from the semiconductor industry. However, these chips feature through-silicon vias (TSVs), which vertically connect multiple dies, and these TSVs may fail, resulting in a decreased yield. Unfortunately, previously proposed methods to repair TSVs cannot handle certain failure patterns. For example, existing techniques cannot repair clustered TSV faults, which commonly occur in practice. Furthermore, the number of signal TSVs typically determines the number of redundant TSVs, which may result in wasteful and redundant TSVs. In this paper, a new TSV repair scheme is proposed that replaces defective TSVs with redundant TSVs by utilizing the architecture of a cube, which can replace any face with any of the other faces. Both signal TSVs and redundant TSVs are placed in the face of cube, so any faulted TSVs can be replaced with redundant TSVs. The experimental results indicate that the new method guarantees 100% coverage with any number of signal TSVs and redundant TSVs.",

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note = "Funding Information: Manuscript received September 21, 2018; revised January 27, 2019 and May 22, 2019; accepted June 26, 2019. Date of publication July 9, 2019; date of current version August 20, 2020. This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea Government (MSIT) under Grant 2019R1A2C3011079. This paper was recommended by Associate Editor X. Li. (Corresponding author: Sungho Kang.) The authors are with the Computer System and Reliable SOC Laboratory, Department of Electrical and Electronic Engineering, Yonsei University, Seoul 03722, South Korea (e-mail: cmh9292@soc.yonsei.ac.kr; keor@soc.yonsei.ac.kr; shkang@yonsei.ac.kr). Digital Object Identifier 10.1109/TCAD.2019.2927485 Publisher Copyright: {\textcopyright} 1982-2012 IEEE.",

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A 3-D Rotation-Based Through-Silicon via Redundancy Architecture for Clustering Faults

Abstract

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All Science Journal Classification (ASJC) codes

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