A 7.5-to-11.1 Gb/s half-rate referenceless clock and data recovery (CDR) with a compact frequency acquisition scheme is proposed. Using the bang-bang phase-frequency detector with a direct up/dn control, the referenceless CDR is realized by a single-loop architecture which performs both phase and frequency acquisition in the same loop. The proposed frequency acquisition scheme achieves a wide capture range of 3.6 Gb/s and reduces cycle-slips. The proposed CDR is fabricated in 65-nm CMOS technology and occupies an active area of 0.04 mm2. At the data rate of 10 Gb/s, the proposed CDR consumes 27.1 mW from 1.3-V supply.
|Title of host publication
|38th Annual Custom Integrated Circuits Conference
|Subtitle of host publication
|A Showcase for Integrated Circuit Design in Silicon Hills, CICC 2017
|Institute of Electrical and Electronics Engineers Inc.
|Published - 2017 Jul 26
|38th Annual Custom Integrated Circuits Conference, CICC 2017 - Austin, United States
Duration: 2017 Apr 30 → 2017 May 3
|Proceedings of the Custom Integrated Circuits Conference
|38th Annual Custom Integrated Circuits Conference, CICC 2017
|17/4/30 → 17/5/3
Bibliographical notePublisher Copyright:
© 2017 IEEE.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering