This brief presents a 2.5-28 Gb/s multi-standard transmitter with a two-step time-multiplexing driver. The proposed two-step time-multiplexing driver not only lowers the output parasitic capacitances but also mitigates charge injection by reducing the number of stacks compared with a 4-to-1 time-multiplexing driver. In addition, the proposed transmitter can enhance the bandwidth by avoiding the use of a 1-unit-interval (1-UI) pulse which is one of the main design challenges in high-speed transmitters. It also provides a controllable output swing and a 3-tap feed-forward equalization (FFE) by turning-on and-off the driver slices. The output impedance is calibrated by a background feedback loop, resulting in a good signal integrity. The prototype chip fabricated in a 65-nm CMOS technology consists of a four-channel transmitter and a global all-digital phase-locked loop (ADPLL). One channel of the transmitter with the ADPLL occupies an active area of 0.23 mm2 and consume 213 mW at 28 Gb/s.
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems II: Express Briefs|
|Publication status||Published - 2019 Dec|
Bibliographical notePublisher Copyright:
© 2004-2012 IEEE.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering