A 240-frames/s 2.1-mpixel CMOS image sensor with column-shared cyclic ADCs

Seunghyun Lim; Jimin Cheon; Youngcheol Chae; Wunki Jung; Dong Hun Lee; Minho Kwon; Kwisung Yoo; Seogheon Ham; Gunhee Han

doi:10.1109/JSSC.2011.2144010

A 240-frames/s 2.1-mpixel CMOS image sensor with column-shared cyclic ADCs

Seunghyun Lim, Jimin Cheon, Youngcheol Chae, Wunki Jung, Dong Hun Lee, Minho Kwon, Kwisung Yoo, Seogheon Ham, Gunhee Han

Research output: Contribution to journal › Article › peer-review

51 Citations (Scopus)

Abstract

This paper proposes a low-power 240 frames/s 2.1 M-pixel CMOS image sensor with column-shared cyclic (CY) ADCs. Two-column shared CY-ADC architecture and two-level stacked ADC placement are employed for low-power and small pixel pitch design. The proposed CY-ADC uses only one OTA and four capacitors. Distributed clocking scheme using cascaded repeaters is proposed to reduce the required peak current. The prototype sensor was fabricated in a 0.13-μm 1P4M process with pixel pitch of 2.25 μm. The designed 10-bit ADC dissipates only 90 μW/channel with 1.5 V supply. The measured DNL and INL are + 0.59/- 0.83 LSB and + 2.8/-3.6 LSB, respectively. The measured maximum pixel rate is 500 Mpixels/s with total power consumption of 300 mW.

Original language	English
Article number	5771069
Pages (from-to)	2073-2083
Number of pages	11
Journal	IEEE Journal of Solid-State Circuits
Volume	46
Issue number	9
DOIs	https://doi.org/10.1109/JSSC.2011.2144010
Publication status	Published - 2011 Sept

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/JSSC.2011.2144010

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title = "A 240-frames/s 2.1-mpixel CMOS image sensor with column-shared cyclic ADCs",

abstract = "This paper proposes a low-power 240 frames/s 2.1 M-pixel CMOS image sensor with column-shared cyclic (CY) ADCs. Two-column shared CY-ADC architecture and two-level stacked ADC placement are employed for low-power and small pixel pitch design. The proposed CY-ADC uses only one OTA and four capacitors. Distributed clocking scheme using cascaded repeaters is proposed to reduce the required peak current. The prototype sensor was fabricated in a 0.13-μm 1P4M process with pixel pitch of 2.25 μm. The designed 10-bit ADC dissipates only 90 μW/channel with 1.5 V supply. The measured DNL and INL are + 0.59/- 0.83 LSB and + 2.8/-3.6 LSB, respectively. The measured maximum pixel rate is 500 Mpixels/s with total power consumption of 300 mW.",

author = "Seunghyun Lim and Jimin Cheon and Youngcheol Chae and Wunki Jung and Lee, {Dong Hun} and Minho Kwon and Kwisung Yoo and Seogheon Ham and Gunhee Han",

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AU - Jung, Wunki

AU - Lee, Dong Hun

AU - Kwon, Minho

AU - Yoo, Kwisung

AU - Ham, Seogheon

AU - Han, Gunhee

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A 240-frames/s 2.1-mpixel CMOS image sensor with column-shared cyclic ADCs

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