TY - GEN
T1 - A 2-Gbps CMOS adaptive line equalizer
AU - Lee, Jae Wook
AU - Lee, Bhum Cheol
AU - Choi, Woo Young
PY - 2004
Y1 - 2004
N2 - A 2-Gbps line equalizer circuit is realized with 0.25 μm CMOS technology. The equalizer is made of input stage buffer, limiter and square difference circuits. The limiter has replica-feedback limiting amplifiers, which do not require common mode feedback. Successful equalization is demonstrated for signals transmitted over 1.5m long PCB trace.
AB - A 2-Gbps line equalizer circuit is realized with 0.25 μm CMOS technology. The equalizer is made of input stage buffer, limiter and square difference circuits. The limiter has replica-feedback limiting amplifiers, which do not require common mode feedback. Successful equalization is demonstrated for signals transmitted over 1.5m long PCB trace.
UR - http://www.scopus.com/inward/record.url?scp=14544290577&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=14544290577&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:14544290577
SN - 078038637X
T3 - Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
SP - 244
EP - 247
BT - Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
T2 - Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
Y2 - 4 August 2004 through 5 August 2004
ER -