A 1.8-3.2-GHz fully differential GaAs MESFET PLL

Tae Sik Cheung, Bhum Cheol Lee, Eun Chang Choi, Woo Young Choi

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)


A 1.8-3.2-GHz fully differential phase-locked loop (PLL) is realized for asynchronous transfer mode clock generation applications. The PLL includes a new differential voltage controlled oscillator with the wide tuning range of 1.74 ∼ 3.40 GHz and a new differential charge pump with improved hold characteristics. The PLL is implemented with 0.5-μm GaAs MESFET technology. The experimental results show that the proposed PLL has a lock range of 1.8 ∼ 3.2 GHz and its output RMS jitter is at most 5.0 ps (0.015 UI) at 3.2 GHz.

Original languageEnglish
Pages (from-to)605-610
Number of pages6
JournalIEEE Journal of Solid-State Circuits
Issue number4
Publication statusPublished - 2001

Bibliographical note

Funding Information:
Manuscript received May 3, 2000; revised December 6, 2000. This work was supported by the Korean Ministry of Information and Communications and by the Brain Korea 21 Project.

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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