A 1.5 v 2 GS/s 82.1 dB-SFDR Track and Hold Circuit Based on the Time-Divided Post-Distortion Cancelation Technique

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Abstract

This brief presents a track and hold (T/H) circuit for time-interleaved analog-To-digital converters based on a new linearization technique-time-divided post-distortion cancellation. Fabricated in 65 nm CMOS, it achieves 82.1 dB SFDR with a 700-mV near-Nyquist input at a clock speed of 2 GS/s, while drawing only 9 mW power from a 1.5-V supply. Compared to the previous state-of-The-Art circuits, this T/H circuit exhibits an energy-efficiency figure-of-merit improvement of 9.5 dB.

Original languageEnglish
Pages (from-to)4719-4723
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume69
Issue number12
DOIs
Publication statusPublished - 2022 Dec 1

Bibliographical note

Publisher Copyright:
© 2004-2012 IEEE.

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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