A 14nm SRAM Using NMOS Header Assist Cell for Improved Write Ability and Reduced Cell Retention Leakage

Jungmyung Kang; Keonhee Cho; Sekeon Kim; Giseok Kim; Hyunjun Kim; Dongwook Seo; Sangyeop Baeck; Seiseung Yoon; Seong Ook Jung

doi:10.1109/ESSERC62670.2024.10719479

A 14nm SRAM Using NMOS Header Assist Cell for Improved Write Ability and Reduced Cell Retention Leakage

Jungmyung Kang, Keonhee Cho, Sekeon Kim, Giseok Kim, Hyunjun Kim, Dongwook Seo, Sangyeop Baeck, Seiseung Yoon, Seong Ook Jung

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

This paper presents NMOS header assist cell (NHAC) that lowers SRAM VMin with minimal power overhead for low power applications. The proposed NHAC, featuring a bitcell-compatible layout, is inserted between cell arrays to provide cell power. NHAC achieves a VMIN improvement of 210 mV with 4% power overhead, even in the high interconnect resistance case, thanks to the continuous self-collapse of cell power voltage. Additionally, enabling all NHACs in sleep mode reduces bitcell retention leakage by 25% to 61% without additional area cost.

Original language	English
Title of host publication	ESSERC 2024 - Proceedings
Subtitle of host publication	50th IEEE European Solid-State Electronics Research Conference
Publisher	IEEE Computer Society
Pages	669-672
Number of pages	4
ISBN (Electronic)	9798350388138
DOIs	https://doi.org/10.1109/ESSERC62670.2024.10719479
Publication status	Published - 2024
Event	50th IEEE European Solid-State Electronics Research Conference, ESSERC 2024 - Bruges, Belgium Duration: 2024 Sept 9 → 2024 Sept 12

Publication series

Name	European Solid-State Circuits Conference
ISSN (Print)	1930-8833

Conference

Conference	50th IEEE European Solid-State Electronics Research Conference, ESSERC 2024
Country/Territory	Belgium
City	Bruges
Period	24/9/9 → 24/9/12

Bibliographical note

Publisher Copyright:
© 2024 IEEE.

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ESSERC62670.2024.10719479

Cite this

Kang, J., Cho, K., Kim, S., Kim, G., Kim, H., Seo, D., Baeck, S., Yoon, S., & Jung, S. O. (2024). A 14nm SRAM Using NMOS Header Assist Cell for Improved Write Ability and Reduced Cell Retention Leakage. In ESSERC 2024 - Proceedings: 50th IEEE European Solid-State Electronics Research Conference (pp. 669-672). (European Solid-State Circuits Conference). IEEE Computer Society. https://doi.org/10.1109/ESSERC62670.2024.10719479

@inproceedings{788a535c6a05404bbfaab98830056254,

title = "A 14nm SRAM Using NMOS Header Assist Cell for Improved Write Ability and Reduced Cell Retention Leakage",

abstract = "This paper presents NMOS header assist cell (NHAC) that lowers SRAM VMin with minimal power overhead for low power applications. The proposed NHAC, featuring a bitcell-compatible layout, is inserted between cell arrays to provide cell power. NHAC achieves a VMIN improvement of 210 mV with 4\% power overhead, even in the high interconnect resistance case, thanks to the continuous self-collapse of cell power voltage. Additionally, enabling all NHACs in sleep mode reduces bitcell retention leakage by 25\% to 61\% without additional area cost.",

keywords = "Static random access memory (SRAM), assist cell, interconnect resistance, nmos header, retention leakage, self-collapse, write assist circuit",

author = "Jungmyung Kang and Keonhee Cho and Sekeon Kim and Giseok Kim and Hyunjun Kim and Dongwook Seo and Sangyeop Baeck and Seiseung Yoon and Jung, \{Seong Ook\}",

note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 50th IEEE European Solid-State Electronics Research Conference, ESSERC 2024 ; Conference date: 09-09-2024 Through 12-09-2024",

year = "2024",

doi = "10.1109/ESSERC62670.2024.10719479",

language = "English",

series = "European Solid-State Circuits Conference",

publisher = "IEEE Computer Society",

pages = "669--672",

booktitle = "ESSERC 2024 - Proceedings",

address = "United States",

}

Kang, J, Cho, K, Kim, S, Kim, G, Kim, H, Seo, D, Baeck, S, Yoon, S & Jung, SO 2024, A 14nm SRAM Using NMOS Header Assist Cell for Improved Write Ability and Reduced Cell Retention Leakage. in ESSERC 2024 - Proceedings: 50th IEEE European Solid-State Electronics Research Conference. European Solid-State Circuits Conference, IEEE Computer Society, pp. 669-672, 50th IEEE European Solid-State Electronics Research Conference, ESSERC 2024, Bruges, Belgium, 24/9/9. https://doi.org/10.1109/ESSERC62670.2024.10719479

A 14nm SRAM Using NMOS Header Assist Cell for Improved Write Ability and Reduced Cell Retention Leakage. / Kang, Jungmyung; Cho, Keonhee; Kim, Sekeon et al.
ESSERC 2024 - Proceedings: 50th IEEE European Solid-State Electronics Research Conference. IEEE Computer Society, 2024. p. 669-672 (European Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A 14nm SRAM Using NMOS Header Assist Cell for Improved Write Ability and Reduced Cell Retention Leakage

AU - Kang, Jungmyung

AU - Cho, Keonhee

AU - Kim, Sekeon

AU - Kim, Giseok

AU - Kim, Hyunjun

AU - Seo, Dongwook

AU - Baeck, Sangyeop

AU - Yoon, Seiseung

AU - Jung, Seong Ook

PY - 2024

Y1 - 2024

N2 - This paper presents NMOS header assist cell (NHAC) that lowers SRAM VMin with minimal power overhead for low power applications. The proposed NHAC, featuring a bitcell-compatible layout, is inserted between cell arrays to provide cell power. NHAC achieves a VMIN improvement of 210 mV with 4% power overhead, even in the high interconnect resistance case, thanks to the continuous self-collapse of cell power voltage. Additionally, enabling all NHACs in sleep mode reduces bitcell retention leakage by 25% to 61% without additional area cost.

AB - This paper presents NMOS header assist cell (NHAC) that lowers SRAM VMin with minimal power overhead for low power applications. The proposed NHAC, featuring a bitcell-compatible layout, is inserted between cell arrays to provide cell power. NHAC achieves a VMIN improvement of 210 mV with 4% power overhead, even in the high interconnect resistance case, thanks to the continuous self-collapse of cell power voltage. Additionally, enabling all NHACs in sleep mode reduces bitcell retention leakage by 25% to 61% without additional area cost.

KW - Static random access memory (SRAM)

KW - assist cell

KW - interconnect resistance

KW - nmos header

KW - retention leakage

KW - self-collapse

KW - write assist circuit

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DO - 10.1109/ESSERC62670.2024.10719479

M3 - Conference contribution

AN - SCOPUS:85208444495

T3 - European Solid-State Circuits Conference

SP - 669

EP - 672

BT - ESSERC 2024 - Proceedings

PB - IEEE Computer Society

T2 - 50th IEEE European Solid-State Electronics Research Conference, ESSERC 2024

Y2 - 9 September 2024 through 12 September 2024

ER -

Kang J, Cho K, Kim S, Kim G, Kim H, Seo D et al. A 14nm SRAM Using NMOS Header Assist Cell for Improved Write Ability and Reduced Cell Retention Leakage. In ESSERC 2024 - Proceedings: 50th IEEE European Solid-State Electronics Research Conference. IEEE Computer Society. 2024. p. 669-672. (European Solid-State Circuits Conference). doi: 10.1109/ESSERC62670.2024.10719479

A 14nm SRAM Using NMOS Header Assist Cell for Improved Write Ability and Reduced Cell Retention Leakage

Abstract

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Bibliographical note

All Science Journal Classification (ASJC) codes

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