A 1.1-pJ/b 8-to-16-Gb/s Receiver With Stochastic CTLE Adaptation

Minkyo Shim, Kwang Hoon Lee, Seungha Roh, Kwanseo Park, Deog Kyoon Jeong

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)


This brief presents an 8-to-16-Gb/s referenceless receiver with a stochastic continuous-time linear equalizer (CTLE) adaptation. The proposed stochastic CTLE gain selector (SCGS) achieves a maximum horizontal eye margin and avoids sub-optimal settling by utilizing sequential edge and data samples. The proposed SCGS detects the optimum CTLE coefficient with the weighted summation of the histograms obtained under various data patterns and channel conditions. The stochastic CTLE adaptation shares the deserialized edge and data samples used for the CDR. Therefore, it does not require additional hardware in the analog domain, achieving low power consumption. The golden weight of the SCGS is obtained through an epsilon-constraint weight searching algorithm. A prototype chip fabricated in 28-nm CMOS technology occupies an active area of 0.029 mm2. The measured CTLE adaptation behavior shows that the maximum eye width is achieved with the proposed SCGS. The prototype chip achieves BER over a channel with 14-dB loss at 8 GHz and consumes 17.7 mW at 16 Gb/s, exhibiting a power efficiency of 1.1 pJ/b.

Original languageEnglish
Pages (from-to)381-385
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Issue number2
Publication statusPublished - 2023 Feb 1

Bibliographical note

Publisher Copyright:
© 2004-2012 IEEE.

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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