A 100 nm copper/low-K bulk CMOS technology with multi Vt and multi gate oxide integrated transistors for low standby power, high performance and RF/analog system on chip applications

Geoffrey C.F. Yeap; J. Chen; P. Grudowski; Y. Jeon; Y. Shiho; W. Qi; S. Jallepalli; N. Ramani; K. Hellig; L. Vishnubhotla; T. Luo; H. Tseng; Y. Du; S. Lim; P. Abramowitz; C. Reddy; S. Parihar; R. Singh; M. Wright; K. Patterson; N. Benavides; D. Bonser; T. V. Gompel; J. Conner; J. J. Lee; M. Rendon; D. Hall; A. Nghiem; R. Stout; K. Weidemann; A. Duvallet; J. Alvis; D. Dyer; D. Burnett; P. Ingersoll; K. Wimmer; S. Veeraraghavan; M. Foisy; M. Hall; J. Pellerin; Dirk Wristers; M. Woo; C. Lage

A 100 nm copper/low-K bulk CMOS technology with multi Vt and multi gate oxide integrated transistors for low standby power, high performance and RF/analog system on chip applications

Geoffrey C.F. Yeap, J. Chen, P. Grudowski, Y. Jeon, Y. Shiho, W. Qi, S. Jallepalli, N. Ramani, K. Hellig, L. Vishnubhotla, T. Luo, H. Tseng, Y. Du, S. Lim, P. Abramowitz, C. Reddy, S. Parihar, R. Singh, M. Wright, K. PattersonN. Benavides, D. Bonser, T. V. Gompel, J. Conner, J. J. Lee, M. Rendon, D. Hall, A. Nghiem, R. Stout, K. Weidemann, A. Duvallet, J. Alvis, D. Dyer, D. Burnett, P. Ingersoll, K. Wimmer, S. Veeraraghavan, M. Foisy, M. Hall, J. Pellerin, Dirk Wristers, M. Woo, C. Lage

Department of Chemical and Biomolecular Engineering

Research output: Contribution to conference › Paper › peer-review

20 Citations (Scopus)

Abstract

We report a 100 nm modular bulk CMOS technology platform with multi Vt and multi gate oxide integrated transistors that enables device and circuit co-design techniques (e.g., well biasing and power down/reduction) for low standby power (LSP), high performance (HP), high speed (HS), and RF/Analog system on chip (SoC) applications. The transistor performances are comparable or better than recently reported data at the 100 nm technology node (see Table 1). This technology also features an all-layer copper/low-k (< 3.0) interlayer dielectric (ILD) backend for speed improvement and dynamic power reduction.

Original language	English
Pages	16-17
Number of pages	2
Publication status	Published - 2002
Event	2002 Symposium on VLSI Technology Digest of Technical Papers - Honolulu, HI, United States Duration: 2002 Jun 11 → 2002 Jun 13

Other

Other	2002 Symposium on VLSI Technology Digest of Technical Papers
Country/Territory	United States
City	Honolulu, HI
Period	02/6/11 → 02/6/13

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

Yeap, G. C. F., Chen, J., Grudowski, P., Jeon, Y., Shiho, Y., Qi, W., Jallepalli, S., Ramani, N., Hellig, K., Vishnubhotla, L., Luo, T., Tseng, H., Du, Y., Lim, S., Abramowitz, P., Reddy, C., Parihar, S., Singh, R., Wright, M., ... Lage, C. (2002). A 100 nm copper/low-K bulk CMOS technology with multi Vt and multi gate oxide integrated transistors for low standby power, high performance and RF/analog system on chip applications. 16-17. Paper presented at 2002 Symposium on VLSI Technology Digest of Technical Papers, Honolulu, HI, United States.

@conference{bc82eabb37364abc9eb75a0217a16b7b,

title = "A 100 nm copper/low-K bulk CMOS technology with multi Vt and multi gate oxide integrated transistors for low standby power, high performance and RF/analog system on chip applications",

abstract = "We report a 100 nm modular bulk CMOS technology platform with multi Vt and multi gate oxide integrated transistors that enables device and circuit co-design techniques (e.g., well biasing and power down/reduction) for low standby power (LSP), high performance (HP), high speed (HS), and RF/Analog system on chip (SoC) applications. The transistor performances are comparable or better than recently reported data at the 100 nm technology node (see Table 1). This technology also features an all-layer copper/low-k (< 3.0) interlayer dielectric (ILD) backend for speed improvement and dynamic power reduction.",

author = "Yeap, {Geoffrey C.F.} and J. Chen and P. Grudowski and Y. Jeon and Y. Shiho and W. Qi and S. Jallepalli and N. Ramani and K. Hellig and L. Vishnubhotla and T. Luo and H. Tseng and Y. Du and S. Lim and P. Abramowitz and C. Reddy and S. Parihar and R. Singh and M. Wright and K. Patterson and N. Benavides and D. Bonser and Gompel, {T. V.} and J. Conner and Lee, {J. J.} and M. Rendon and D. Hall and A. Nghiem and R. Stout and K. Weidemann and A. Duvallet and J. Alvis and D. Dyer and D. Burnett and P. Ingersoll and K. Wimmer and S. Veeraraghavan and M. Foisy and M. Hall and J. Pellerin and Dirk Wristers and M. Woo and C. Lage",

year = "2002",

language = "English",

pages = "16--17",

note = "2002 Symposium on VLSI Technology Digest of Technical Papers ; Conference date: 11-06-2002 Through 13-06-2002",

}

Yeap, GCF, Chen, J, Grudowski, P, Jeon, Y, Shiho, Y, Qi, W, Jallepalli, S, Ramani, N, Hellig, K, Vishnubhotla, L, Luo, T, Tseng, H, Du, Y, Lim, S, Abramowitz, P, Reddy, C, Parihar, S, Singh, R, Wright, M, Patterson, K, Benavides, N, Bonser, D, Gompel, TV, Conner, J, Lee, JJ, Rendon, M, Hall, D, Nghiem, A, Stout, R, Weidemann, K, Duvallet, A, Alvis, J, Dyer, D, Burnett, D, Ingersoll, P, Wimmer, K, Veeraraghavan, S, Foisy, M, Hall, M, Pellerin, J, Wristers, D, Woo, M & Lage, C 2002, 'A 100 nm copper/low-K bulk CMOS technology with multi Vt and multi gate oxide integrated transistors for low standby power, high performance and RF/analog system on chip applications', Paper presented at 2002 Symposium on VLSI Technology Digest of Technical Papers, Honolulu, HI, United States, 02/6/11 - 02/6/13 pp. 16-17.

A 100 nm copper/low-K bulk CMOS technology with multi Vt and multi gate oxide integrated transistors for low standby power, high performance and RF/analog system on chip applications. / Yeap, Geoffrey C.F.; Chen, J.; Grudowski, P. et al.
2002. 16-17 Paper presented at 2002 Symposium on VLSI Technology Digest of Technical Papers, Honolulu, HI, United States.

Research output: Contribution to conference › Paper › peer-review

TY - CONF

T1 - A 100 nm copper/low-K bulk CMOS technology with multi Vt and multi gate oxide integrated transistors for low standby power, high performance and RF/analog system on chip applications

AU - Yeap, Geoffrey C.F.

AU - Chen, J.

AU - Grudowski, P.

AU - Jeon, Y.

AU - Shiho, Y.

AU - Qi, W.

AU - Jallepalli, S.

AU - Ramani, N.

AU - Hellig, K.

AU - Vishnubhotla, L.

AU - Luo, T.

AU - Tseng, H.

AU - Du, Y.

AU - Lim, S.

AU - Abramowitz, P.

AU - Reddy, C.

AU - Parihar, S.

AU - Singh, R.

AU - Wright, M.

AU - Patterson, K.

AU - Benavides, N.

AU - Bonser, D.

AU - Gompel, T. V.

AU - Conner, J.

AU - Lee, J. J.

AU - Rendon, M.

AU - Hall, D.

AU - Nghiem, A.

AU - Stout, R.

AU - Weidemann, K.

AU - Duvallet, A.

AU - Alvis, J.

AU - Dyer, D.

AU - Burnett, D.

AU - Ingersoll, P.

AU - Wimmer, K.

AU - Veeraraghavan, S.

AU - Foisy, M.

AU - Hall, M.

AU - Pellerin, J.

AU - Wristers, Dirk

AU - Woo, M.

AU - Lage, C.

PY - 2002

Y1 - 2002

N2 - We report a 100 nm modular bulk CMOS technology platform with multi Vt and multi gate oxide integrated transistors that enables device and circuit co-design techniques (e.g., well biasing and power down/reduction) for low standby power (LSP), high performance (HP), high speed (HS), and RF/Analog system on chip (SoC) applications. The transistor performances are comparable or better than recently reported data at the 100 nm technology node (see Table 1). This technology also features an all-layer copper/low-k (< 3.0) interlayer dielectric (ILD) backend for speed improvement and dynamic power reduction.

AB - We report a 100 nm modular bulk CMOS technology platform with multi Vt and multi gate oxide integrated transistors that enables device and circuit co-design techniques (e.g., well biasing and power down/reduction) for low standby power (LSP), high performance (HP), high speed (HS), and RF/Analog system on chip (SoC) applications. The transistor performances are comparable or better than recently reported data at the 100 nm technology node (see Table 1). This technology also features an all-layer copper/low-k (< 3.0) interlayer dielectric (ILD) backend for speed improvement and dynamic power reduction.

UR - http://www.scopus.com/inward/record.url?scp=0036045178&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0036045178&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0036045178

SP - 16

EP - 17

T2 - 2002 Symposium on VLSI Technology Digest of Technical Papers

Y2 - 11 June 2002 through 13 June 2002

ER -

A 100 nm copper/low-K bulk CMOS technology with multi Vt and multi gate oxide integrated transistors for low standby power, high performance and RF/analog system on chip applications

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