A 10-Gb/s power and area efficient clock and data recovery circuit in 65-nm CMOS technology

Jinsoo Rhim; Kwang Chun Choi; Woo Young Choi

doi:10.1109/ISOCC.2012.6407050

A 10-Gb/s power and area efficient clock and data recovery circuit in 65-nm CMOS technology

Jinsoo Rhim, Kwang Chun Choi, Woo Young Choi

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

This paper reports a 10-Gb/s power and area efficient clock and data recovery circuit implemented in 65-nm CMOS technology. CMOS static circuits are used as much as possible so that the power consumption and the chip area can be minimized. In order to alleviate the supply sensitivity of CMOS static circuits, a supply-regulator is implemented. At 10-Gb/s, the clock and data recovery circuit consumes 5-mW of power and occupies 0.0075mm² of area.

Original language	English
Title of host publication	ISOCC 2012 - 2012 International SoC Design Conference
Pages	104-107
Number of pages	4
DOIs	https://doi.org/10.1109/ISOCC.2012.6407050
Publication status	Published - 2012
Event	2012 International SoC Design Conference, ISOCC 2012 - Jeju Island, Korea, Republic of Duration: 2012 Nov 4 → 2012 Nov 7

Publication series

Name	ISOCC 2012 - 2012 International SoC Design Conference

Other

Other	2012 International SoC Design Conference, ISOCC 2012
Country/Territory	Korea, Republic of
City	Jeju Island
Period	12/11/4 → 12/11/7

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/ISOCC.2012.6407050

Cite this

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title = "A 10-Gb/s power and area efficient clock and data recovery circuit in 65-nm CMOS technology",

abstract = "This paper reports a 10-Gb/s power and area efficient clock and data recovery circuit implemented in 65-nm CMOS technology. CMOS static circuits are used as much as possible so that the power consumption and the chip area can be minimized. In order to alleviate the supply sensitivity of CMOS static circuits, a supply-regulator is implemented. At 10-Gb/s, the clock and data recovery circuit consumes 5-mW of power and occupies 0.0075mm2 of area.",

author = "Jinsoo Rhim and Choi, {Kwang Chun} and Choi, {Woo Young}",

year = "2012",

doi = "10.1109/ISOCC.2012.6407050",

language = "English",

isbn = "9781467329880",

series = "ISOCC 2012 - 2012 International SoC Design Conference",

pages = "104--107",

booktitle = "ISOCC 2012 - 2012 International SoC Design Conference",

note = "2012 International SoC Design Conference, ISOCC 2012 ; Conference date: 04-11-2012 Through 07-11-2012",

}

Rhim, J, Choi, KC & Choi, WY 2012, A 10-Gb/s power and area efficient clock and data recovery circuit in 65-nm CMOS technology. in ISOCC 2012 - 2012 International SoC Design Conference., 6407050, ISOCC 2012 - 2012 International SoC Design Conference, pp. 104-107, 2012 International SoC Design Conference, ISOCC 2012, Jeju Island, Korea, Republic of, 12/11/4. https://doi.org/10.1109/ISOCC.2012.6407050

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T1 - A 10-Gb/s power and area efficient clock and data recovery circuit in 65-nm CMOS technology

AU - Rhim, Jinsoo

AU - Choi, Kwang Chun

AU - Choi, Woo Young

PY - 2012

Y1 - 2012

N2 - This paper reports a 10-Gb/s power and area efficient clock and data recovery circuit implemented in 65-nm CMOS technology. CMOS static circuits are used as much as possible so that the power consumption and the chip area can be minimized. In order to alleviate the supply sensitivity of CMOS static circuits, a supply-regulator is implemented. At 10-Gb/s, the clock and data recovery circuit consumes 5-mW of power and occupies 0.0075mm2 of area.

AB - This paper reports a 10-Gb/s power and area efficient clock and data recovery circuit implemented in 65-nm CMOS technology. CMOS static circuits are used as much as possible so that the power consumption and the chip area can be minimized. In order to alleviate the supply sensitivity of CMOS static circuits, a supply-regulator is implemented. At 10-Gb/s, the clock and data recovery circuit consumes 5-mW of power and occupies 0.0075mm2 of area.

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U2 - 10.1109/ISOCC.2012.6407050

DO - 10.1109/ISOCC.2012.6407050

M3 - Conference contribution

AN - SCOPUS:84873945229

SN - 9781467329880

T3 - ISOCC 2012 - 2012 International SoC Design Conference

SP - 104

EP - 107

BT - ISOCC 2012 - 2012 International SoC Design Conference

T2 - 2012 International SoC Design Conference, ISOCC 2012

Y2 - 4 November 2012 through 7 November 2012

ER -

A 10-Gb/s power and area efficient clock and data recovery circuit in 65-nm CMOS technology

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