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A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS
Kwanseo Park, Woorham Bae, Haram Ju, Jinhyung Lee, Gyu Seob Jeong, Yoonsoo Kim, Deog Kyoon Jeong
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
3
Citations
(Scopus)