A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS

Kwanseo Park; Woorham Bae; Haram Ju; Jinhyung Lee; Gyu Seob Jeong; Yoonsoo Kim; Deog Kyoon Jeong

doi:10.1109/ISCAS.2015.7169165

A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS

Kwanseo Park, Woorham Bae, Haram Ju, Jinhyung Lee, Gyu Seob Jeong, Yoonsoo Kim, Deog Kyoon Jeong

School of System & Semiconductor Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Citations (Scopus)

Abstract

A 10 Gb/s PLL-based forwarded clock receiver is implemented in 65-nm CMOS technology. The proposed architecture uses a hybrid PLL-based deskew which is combined with a PLL and a DLL. The PLL provides jitter filtering and the DLL performs deskewing by shifting the divided clocks. Since the operating frequency of the DLL is low, the power consumption of the DLL can be reduced. The measurement results show that the rms jitter of the recovered clock is only 576.7 fs which is quite low for a ring-oscillator-based PLL. The receiver chip occupies an active area of 0.0136 mm² and consumes 22.1 mW at the data rate of 10 Gb/s.

Original language	English
Title of host publication	2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	2389-2392
Number of pages	4
ISBN (Electronic)	9781479983919
DOIs	https://doi.org/10.1109/ISCAS.2015.7169165
Publication status	Published - 2015 Jul 27
Event	IEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal Duration: 2015 May 24 → 2015 May 27

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2015-July
ISSN (Print)	0271-4310

Conference

Conference	IEEE International Symposium on Circuits and Systems, ISCAS 2015
Country/Territory	Portugal
City	Lisbon
Period	15/5/24 → 15/5/27

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2015.7169165

Cite this

Park, K., Bae, W., Ju, H., Lee, J., Jeong, G. S., Kim, Y., & Jeong, D. K. (2015). A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS. In 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015 (pp. 2389-2392). Article 7169165 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2015-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2015.7169165

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title = "A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS",

abstract = "A 10 Gb/s PLL-based forwarded clock receiver is implemented in 65-nm CMOS technology. The proposed architecture uses a hybrid PLL-based deskew which is combined with a PLL and a DLL. The PLL provides jitter filtering and the DLL performs deskewing by shifting the divided clocks. Since the operating frequency of the DLL is low, the power consumption of the DLL can be reduced. The measurement results show that the rms jitter of the recovered clock is only 576.7 fs which is quite low for a ring-oscillator-based PLL. The receiver chip occupies an active area of 0.0136 mm2 and consumes 22.1 mW at the data rate of 10 Gb/s.",

author = "Kwanseo Park and Woorham Bae and Haram Ju and Jinhyung Lee and Jeong, {Gyu Seob} and Yoonsoo Kim and Jeong, {Deog Kyoon}",

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Park, K, Bae, W, Ju, H, Lee, J, Jeong, GS, Kim, Y & Jeong, DK 2015, A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS. in 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015., 7169165, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2015-July, Institute of Electrical and Electronics Engineers Inc., pp. 2389-2392, IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, 15/5/24. https://doi.org/10.1109/ISCAS.2015.7169165

A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS. / Park, Kwanseo; Bae, Woorham; Ju, Haram et al.
2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 2389-2392 7169165 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2015-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Ju, Haram

AU - Lee, Jinhyung

AU - Jeong, Gyu Seob

AU - Kim, Yoonsoo

AU - Jeong, Deog Kyoon

PY - 2015/7/27

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N2 - A 10 Gb/s PLL-based forwarded clock receiver is implemented in 65-nm CMOS technology. The proposed architecture uses a hybrid PLL-based deskew which is combined with a PLL and a DLL. The PLL provides jitter filtering and the DLL performs deskewing by shifting the divided clocks. Since the operating frequency of the DLL is low, the power consumption of the DLL can be reduced. The measurement results show that the rms jitter of the recovered clock is only 576.7 fs which is quite low for a ring-oscillator-based PLL. The receiver chip occupies an active area of 0.0136 mm2 and consumes 22.1 mW at the data rate of 10 Gb/s.

AB - A 10 Gb/s PLL-based forwarded clock receiver is implemented in 65-nm CMOS technology. The proposed architecture uses a hybrid PLL-based deskew which is combined with a PLL and a DLL. The PLL provides jitter filtering and the DLL performs deskewing by shifting the divided clocks. Since the operating frequency of the DLL is low, the power consumption of the DLL can be reduced. The measurement results show that the rms jitter of the recovered clock is only 576.7 fs which is quite low for a ring-oscillator-based PLL. The receiver chip occupies an active area of 0.0136 mm2 and consumes 22.1 mW at the data rate of 10 Gb/s.

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Park K, Bae W, Ju H, Lee J, Jeong GS, Kim Y et al. A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS. In 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 2389-2392. 7169165. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS.2015.7169165

A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS

Abstract

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