TY - GEN
T1 - A 0.5V 20fJ/conversion-step rail-to-rail SAR ADC with programmable time-delayed control units for low-power biomedical application
AU - Chang, Sun Il
AU - Al-Ashmouny, Khaled
AU - Yoon, Euisik
PY - 2011
Y1 - 2011
N2 - We report a 0.5V 20fJ/c-s 8bit rail-to-rail SAR ADC realized in 0.25μm technology in a small area of 0.041mm2. For the low-power operation, voltage-scalable single-clock (LVS) bootstrap circuitry and a programmable time-delayed control unit have been proposed and implemented. The measured FOM is 20fJ/c-s at 31.25 kS/s with SNDR of 45.14 dB. The proposed ADC can boost the input range to extend its full-scale range above the rail by one bit without any additional hardware.
AB - We report a 0.5V 20fJ/c-s 8bit rail-to-rail SAR ADC realized in 0.25μm technology in a small area of 0.041mm2. For the low-power operation, voltage-scalable single-clock (LVS) bootstrap circuitry and a programmable time-delayed control unit have been proposed and implemented. The measured FOM is 20fJ/c-s at 31.25 kS/s with SNDR of 45.14 dB. The proposed ADC can boost the input range to extend its full-scale range above the rail by one bit without any additional hardware.
UR - http://www.scopus.com/inward/record.url?scp=82955164411&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=82955164411&partnerID=8YFLogxK
U2 - 10.1109/ESSCIRC.2011.6044976
DO - 10.1109/ESSCIRC.2011.6044976
M3 - Conference contribution
AN - SCOPUS:82955164411
SN - 9781457707018
T3 - European Solid-State Circuits Conference
SP - 339
EP - 342
BT - ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference
T2 - 37th European Solid-State Circuits Conference, ESSCIRC 2011
Y2 - 12 September 2011 through 16 September 2011
ER -